參數(shù)資料
型號(hào)： AD9852/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/52頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9852
設(shè)計(jì)資源： AD9852 Eval Brd BOM
AD9852 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
類型： 合成器
適用于相關(guān)產(chǎn)品： AD9852
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AD9852ASTZ-ND - IC DDS SYNTHESIZER CMOS 80-LQFP
AD9852
Rev. E | Page 10 of 52
Pin Number
Mnemonic
Description
19
A0/SDIO
Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/Bidirectional Serial Data Input/Output. A0 is used only in parallel programming
mode. SDIO is used in 2-wire serial communication mode.
20
I/O UD CLK
Bidirectional I/O Update Clock. Direction is selected in control register. If selected as an input, a
rising edge transfers the contents of the I/O port buffers to the programming registers. If I/O UD
CLK is selected as an output (default), an output pulse (low to high) with a duration of eight
system clock cycles indicates that an internal frequency update has occurred.
21
WR/SCLK
Write Parallel Data to I/O Port Buffers. Shared function with SCLK. Serial clock signal associated
with the serial programming bus. Data is registered on the rising edge. This pin is shared with
WR when the parallel mode is selected. The mode is dependent on Pin 70 (S/P SELECT).
22
RD/CS
Read Parallel Data from Programming Registers. Shared function with CS. Chip select signal
associated with the serial programming bus. Active low. This pin is shared with RD when the
parallel mode is selected.
29
FSK/BPSK/HOLD
Multifunction Pin. Functions according to the mode of operation selected in the programming
control register. If in the FSK mode, logic low selects F1 and logic high selects F2. If in the BPSK
mode, logic low selects Phase 1 and logic high selects Phase 2. In chirp mode, logic high
engages the hold function, causing the frequency accumulator to halt at its current location. To
resume or commence chirp, logic low is asserted.
30
OSK
Output Shaped Keying. Must first be selected in the programming control register to function.
A logic high causes the cosine DAC outputs to ramp up from zero-scale to full-scale amplitude
at a preprogrammed rate. Logic low causes the full-scale output to ramp down to zero scale at
the preprogrammed rate.
31, 32, 37, 38, 44, 50, 54,
60, 65
AVDD
Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND.
33, 34, 39, 40, 41, 45, 46,
47, 53, 59, 62, 66, 67
AGND
Connections for Analog Circuitry Ground Return. Same potential as DGND.
36
VOUT
Noninverted Output of the Internal High Speed Comparator. Designed to drive 10 dBm to 50 Ω
loads as well as standard CMOS logic levels.
42
VINP
Voltage Input Positive. The noninverting input of the internal high speed comparator.
43
VINN
Voltage Input Negative. The inverting input of the internal high speed comparator.
48
IOUT1
Unipolar Current Output of the Cosine DAC (refer to Figure 3).
49
IOUT1
Complementary Unipolar Current Output of the Cosine DAC.
51
IOUT2
Complementary Unipolar Current Output of the Control DAC.
52
IOUT2
Unipolar Current Output of the Control DAC.
55
DACBP
Common Bypass Capacitor Connection for Both DACs. A 0.01 μF chip capacitor from this pin to
AVDD improves harmonic distortion and SFDR slightly. No connect is permissible, but results in
a slight degradation in SFDR.
56
DAC RSET
Common Connection for Both DACs. Used to set the full-scale output current. RSET = 39.9/ IOUT.
Normal RSET range is from 8 kΩ (5 mA) to 2 kΩ (20 mA).
61
PLL FILTER
Connection for the External Zero-Compensation Network of the REFCLK Multiplier’s PLL Loop
Filter. The zero-compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF
capacitor. The other side of the network should be connected to AVDD as close as possible to
Pin 60. For optimum phase noise performance, the REFCLK multiplier can be bypassed by
setting the bypass PLL bit in Control Register 1E hex.
64
DIFF CLK ENABLE
Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK
and REFCLK (Pin 69 and Pin 68, respectively).
68
REFCLK
Complementary (180° Out of Phase) Differential Clock Signal. User should tie this pin high or
low when single-ended clock mode is selected. Same signal levels as REFCLK.
69
REFCLK
Single-Ended (CMOS Logic Levels Required) Reference Clock Input or One of Two Differential
Clock Signals. In differential reference clock mode, both inputs can be CMOS logic levels or have
greater than 400 mV p-p square or sine waves centered about 1.6 V dc.
70
S/P SELECT
Selects between serial programming mode (logic low) and parallel programming mode
(logic high).
71
MASTER RESET
Initializes the serial/parallel programming bus to prepare for user programming, and sets
programming registers to a do-nothing state defined by the default values listed in Table 9.
Active on logic high. Asserting this pin is essential for proper operation upon power-up.
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