參數(shù)資料
型號(hào)： AD9852/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/52頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9852
設(shè)計(jì)資源： AD9852 Eval Brd BOM
AD9852 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
類(lèi)型： 合成器
適用于相關(guān)產(chǎn)品： AD9852
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AD9852ASTZ-ND - IC DDS SYNTHESIZER CMOS 80-LQFP
AD9852
Rev. E | Page 34 of 52
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases of a serial communication cycle with the
AD9852. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9852 coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9852 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the next
data transfer is a read or write and the register address to be
acted upon.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9852. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9852
and the system controller. The number of data bytes transferred
during Phase 2 of the communication cycle is a function of the
register address. The AD9852 internal serial I/O controller
expects every byte of the register being accessed to be
transferred. Table 11 describes how many bytes must be
transferred.
Table 11. Register Address vs. Data Bytes Transferred
Serial
Register
Address
Register Name
Number
of Bytes
Transferred
0
Phase Offset Tuning Word Register 1
2
1
Phase Offset Tuning Word Register 2
2
Frequency Tuning Word 1
6
3
Frequency Tuning Word 2
6
4
Delta frequency register
6
5
Update clock rate register
4
6
Ramp rate clock register
3
7
Control register
4
8
Digital multiplier register
2
A
On/off output shaped keying ramp
rate register
1
B
Control DAC register
2
At the completion of a communication cycle, the AD9852 serial
port controller expects the subsequent eight rising SCLK edges
to be the instruction byte of the next communication cycle. In
addition, an active high input on the IO RESET pin immediately
terminates the current communication cycle. After IO RESET
returns low, the AD9852 serial port controller requires the sub-
sequent eight rising SCLK edges to be the instruction byte of
the next communication cycle.
All data input to the AD9852 is registered on the rising edge of
SCLK, and all data is driven out of the AD9852 on the falling
edge of SCLK.
Figure 51 and Figure 52 are useful in understanding the general
operation of the AD9852 serial port.
INSTRUCTION
CYCLE
DATA TRANSFER
INSTRUCTION
BYTE
DATA BYTE 1
DATA BYTE 2
DATA BYTE 3
SDIO
CS
00634-051
Figure 51. Using SDIO as a Read/Write Transfer
INSTRUCTION
CYCLE
DATA TRANSFER
INSTRUCTION
BYTE
SDIO
CS
DATA TRANSFER
DATA BYTE 1
DATA BYTE 2
DATA BYTE 3
SDO
00634-052
Figure 52. Using SDIO as an Input and SDO as an Output
INSTRUCTION BYTE
The instruction byte contains the following information:
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
A3
A2
A1
A0
R/W—Bit 7 of the instruction byte determines whether a read
or write data transfer occurs following the instruction byte.
Logic high indicates that a read operation will occur. Logic 0
indicates that a write operation will occur.
Bit 6, Bit 5, and Bit 4 of the instruction byte are dummy bits
(don’t care).
A3, A2, A1, A0—Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction
byte determine which register is accessed during the data transfer
portion of the communication cycle (see Table 9 for register
address details).
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