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參數資料
| 型號： | AD9852/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 13/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9852 |
| 設計資源： | AD9852 Eval Brd BOM AD9852 Schematic |
| 標準包裝： | 1 |
| 系列： | AgileRF™ |
| 類型： | 合成器 |
| 適用于相關產品： | AD9852 |
| 相關產品： | AD9852ASVZ-ND - IC DDS SYNTHESIZER CMOS 80-TQFP AD9852ASTZ-ND - IC DDS SYNTHESIZER CMOS 80-LQFP |
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AD9852
Rev. E | Page 20 of 52
I/O UD CLK
F1
F2
0
FREQUENCY
MODE
TW1
TW2
010 (RAMPED FSK)
F1
F2
000 (DEFAULT)
0
REQUIRES A POSITIVE TWOS COMPLEMENT VALUE
RAMP RATE
DFW
FSK DATA (PIN 29)
00634-034
Figure 34. Ramped FSK Mode (Start at F1)
F1
F2
0
FREQUENCY
MODE
TW1
TW2
FSK DATA (PIN 29)
010 (RAMPED FSK)
F1
F2
000 (DEFAULT)
0
I/O UD CLK
00634-035
Figure 35. Ramped FSK Mode (Start at F2)
The purpose of ramped FSK is to provide better bandwidth
containment than can be achieved using traditional FSK. In
ramped FSK, the instantaneous frequency changes of traditional
FSK are replaced with more gradual, user-defined frequency
changes. The dwell time at F1 and F2 can be equal to or much
greater than the time spent at each intermediate frequency. The
user controls the dwell time at F1 and F2, the number of
intermediate frequencies, and the time spent at each frequency.
Unlike unramped FSK, ramped FSK requires the lowest
frequency to be loaded into the F1 registers and the highest
frequency to be loaded into the F2 registers.
Several registers must be programmed to instruct the DDS
regarding the resolution of intermediate frequency steps (48 bits)
and the time spent at each step (20 bits). Furthermore, the CLR
ACC1 bit in the control register should be toggled (low-high-low)
prior to operation to ensure that the frequency accumulator is
starting from an all 0s output condition.
For piecewise, nonlinear frequency transitions, it is necessary
to reprogram the registers while the frequency transition is in
progress to affect the desired response.
Parallel Register Address 1A hex to Parallel Register Address 1C
hex comprise the 20-bit ramp rate clock registers. This is a
countdown counter that outputs a single pulse whenever the
count reaches 0. The counter is activated any time a logic level
change occurs on the FSK input (Pin 29). This counter is run at
the system clock rate, 300 MHz maximum. The time period
between each output pulse is
(N + 1) × System Clock Period
where N is the 20-bit ramp rate clock value programmed by
the user.
The allowable range of N is from 1 to (220 1). The output of
this counter clocks the 48-bit frequency accumulator shown in
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