參數(shù)資料
型號: ADSP-21469KBCZ-3
廠商: Analog Devices Inc
文件頁數(shù): 36/72頁
文件大?。?/td> 0K
描述: IC DSP 32/40BIT 400MHZ 324BGA
產(chǎn)品變化通告: Pin Function Change 08/Mar/2012
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: DAI,DPI,EBI/EMI,I²C,SCI,SPI,SSP,UART/USART
時(shí)鐘速率: 400MHz
非易失內(nèi)存: 外部
芯片上RAM: 5Mb
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.05V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 324-BGA,CSPBGA
供應(yīng)商設(shè)備封裝: 324-CSPBGA
包裝: 托盤
ADSP-21469
Rev. 0
|
Page 41 of 72
|
June 2010
The SPORTx_TDV_O output signal (routing unit) becomes
active in SPORT multichannel mode. During transmit slots
(enabled with active channel selection registers) the
SPORTx_TDV_O is asserted for communication with external
devices.
Table 37. Serial Ports—TDV (Transmit Data Valid)
Parameter
Min
Max
Unit
Switching Characteristics1
tDRDVEN
Data-Valid Enable Delay from Drive Edge of External Clock
3
ns
tDFDVEN
Data-Valid Disable Delay from Drive Edge of External Clock
8
ns
tDRDVIN
Data-Valid Enable Delay from Drive Edge of Internal Clock
–0.1
ns
tDFDVIN
Data-Valid Disable Delay from Drive Edge of Internal Clock
2
ns
1 Referenced to drive edge.
Figure 26. Serial Ports—Transmit Data Valid Internal and External Clock
DRIVE EDGE
DAI_P20–1
(SCLK, EXT)
tDRDVEN
tDFDVEN
DRIVE EDGE
DAI_P20–1
(SCLK, INT)
tDRDVIN
tDFDVIN
TDVx
DAI_P20-1
TDVx
DAI_P20-1
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ADSP-21469KBCZ-4 功能描述:IC DSP 32/40BIT 450MHZ 324BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號處理器) 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C,McASP,McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA(27x27) 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP21469KBCZENG 制造商:Analog Devices 功能描述:
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ADSP-21469KBCZ-X 制造商:Analog Devices 功能描述:FXD PT PROC - Trays
ADSP-21469KBZ-EN 制造商:Analog Devices 功能描述: