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參數(shù)資料
| 型號： | ADSP-21469KBCZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 32/40BIT 400MHZ 324BGA |
| 產品變化通告： | Pin Function Change 08/Mar/2012 |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART |
| 時鐘速率： | 400MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.05V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA，CSPBGA |
| 供應商設備封裝： | 324-CSPBGA |
| 包裝： | 托盤 |
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Rev. 0
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Page 12 of 72
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June 2010
ADSP-21469
PIN FUNCTION DESCRIPTIONS
UNUSED DDR2 PINS
When the DDR2 controller is not used:
Leave the DDR2 signal pins floating.
Internally, three-state the DDR2 I/O signals. This can be
done by setting the DIS_DDRCTL bit of DDR2CTL0
register.
Power down the receive path by setting the PWD bits of the
DDR2PADCTLx register.
Connect the VDD_DDR2 pins to the VDD_INT supply.
Leave VREF floating/unconnected.
Table 9. Pin Descriptions
Name
Type
State During/
After Reset
Description
AMI_ADDR23–0
I/O/T (ipu)
High-Z/driven
low (boot)
External Address. The
processor outputs addresses for external memory and
peripherals on these pins. The data pins can be multiplexed to support the PDAP (I)
and PWM (O). After reset, all AMI_ADDR23–0 pins are in external memory interface
mode and FLAG(0–3) pins are in FLAGS mode (default). When configured in the
IDP_PDAP_CTL register, IDP channel 0 scans the AMI_ADDR23–0 pins for parallel input
data. Unused AMI pins can be left unconnected.
AMI_DATA7–0
I/O/T (ipu)
High-Z
External Data. The data pins can be multiplexed to support the external memory
interface data (I/O), the PDAP (I), FLAGS (I/O) and PWM (O). After reset, all AMI_DATA
pins are in EMIF mode and FLAG(0-3) pins are in FLAGS mode (default). Unused AMI
pins can be left unconnected.
AMI_ACK
I (ipu)
Memory Acknowledge (AMI_ACK). External devices can deassert AMI_ACK (low) to
add wait states to an external memory access. AMI_ACK is used by I/O devices,
memory controllers, or other peripherals to hold off completion of an external
memory access. Unused AMI pins can be left unconnected.
AMI_MS0–1
O/T (ipu)
High-Z
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-
sponding banks of external memory on the AMI interface. The MS1-0 lines are
decoded memory address lines that change at the same time as the other address
lines. When no external memory access is occurring the MS1-0 lines are inactive; they
are active however when a conditional memory access instruction is executed,
whether or not the condition is true. Unused AMI pins can be left unconnected.
The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the
ADSP-214xx SHARC Processor Hardware Reference.
AMI_RD
O/T (ipu)
High-Z
AMI Port Read Enable. AMI_RD is asserted whenever the
processor reads a word
from external memory.
AMI_WR
O/T (ipu)
High-Z
External Port Write Enable. AMI_WR is asserted when the processor writes a word
to external memory.
FLAG[0]/IRQ0
I/O (ipu)
FLAG[0] INPUT
FLAG0/Interrupt Request0.
FLAG[1]/IRQ1
I/O (ipu)
FLAG[1] INPUT
FLAG1/Interrupt Request1.
FLAG[2]/IRQ2/
AMI_MS2
I/O (ipu)
FLAG[2] INPUT
FLAG2/Interrupt Request2/Async Memory Select2.
FLAG[3]/TMREXP/
AMI_MS3
I/O (ipu)
FLAG[3] INPUT
FLAG3/Timer Expired/Async Memory Select3.
The following symbols appear in the Type column of Table 9: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k
–63 k. The range
of an ipd resistor can be between 31 k
–85 k.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.
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| ADSP-21469KBCZ-4 | 功能描述:IC DSP 32/40BIT 450MHZ 324BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP21469KBCZENG | 制造商:Analog Devices 功能描述: |
| ADSP-21469KBCZ-ENG | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBCZ-X | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBZ-EN | 制造商:Analog Devices 功能描述: |
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