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參數(shù)資料
| 型號(hào)： | ADSP-21469KBCZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 72/72頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DSP 32/40BIT 400MHZ 324BGA |
| 產(chǎn)品變化通告： | Pin Function Change 08/Mar/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類(lèi)型： | 浮點(diǎn) |
| 接口： | DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART |
| 時(shí)鐘速率： | 400MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.05V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 324-CSPBGA |
| 包裝： | 托盤(pán) |
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ADSP-21469
Rev. 0
|
Page 9 of 72
|
June 2010
Input Data Port
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I2S, left-justified sample pair, or right-justified
mode. One frame sync cycle indicates one 64-bit left/right pair,
but data is sent to the FIFO as 32-bit words (that is, one-half of a
frame at a time). The processor supports 24- and 32-bit I2S, 24-
and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-
justified formats.
Precision Clock Generators
The precision clock generators (PCG) consist of four units—A,
B, C, and D, each of which generates a pair of signals (clock and
frame sync) derived from a clock input signal. The units are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface (SPI) ports, one universal asynchro-
nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), and two general-purpose timers. The DPI includes the
peripherals described in the following sections.
Serial Peripheral Interface
The ADSP-21469 SHARC processors contain two serial periph-
eral interface ports (SPI). The SPI is an industry-standard
synchronous serial link, enabling the SPI-compatible port to
communicate with other SPI compatible devices. The SPI con-
sists of two data pins, one device select pin, and one clock pin. It
is a full-duplex synchronous serial interface, supporting both
master and slave modes. The SPI port can operate in a multi-
master environment by interfacing with up to four other
SPI-compatible devices, either acting as a master or slave device.
The SPI-compatible peripheral implementation also features
programmable baud rate, clock phase, and polarities. The SPI-
compatible port uses open-drain drivers to support a multimas-
ter configuration and to avoid data contention.
UART Port
The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capa-
bility using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface
standard. The UART port also includes support for 5 to 8 data
bits, 1 or 2 stop bits, and none, even, or odd parity. The UART
port supports two modes of operation:
PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
DMA (direct memory access) – The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory.
Timers
The ADSP-21469 has a total of three timers: a core timer that
can generate periodic software interrupts and two general-
purpose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
Pulse waveform generation mode
Pulse width count/capture mode
External event watchdog mode
The core timer can be configured to use FLAG3 as a timer
expired signal, and each general-purpose timer has one bidirec-
tional pin and four registers that implement its mode of
operation. A single control and status register enables or dis-
ables both general-purpose timers independently.
2-Wire Interface Port (TWI)
The TWI is a bidirectional, 2-wire serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI master incorporates the following features:
7-bit addressing
Simultaneous master and slave operation on multiple
device systems with support for multi master data
arbitration
Digital filtering and timed event processing
100 kbps and 400 kbps data rates
Low interrupt rate
I/O Processor Features
Automotive versions of the ADSP-21469 I/O processor provide
67 channels of DMA, while standard versions provide 36 chan-
nels of DMA, as well as an extensive set of peripherals that are
described in the following sections.
DMA Controller
The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously exe-
cuting its program instructions. DMA transfers can occur
between the ADSP-21469’s internal memory and its serial ports,
the SPI-compatible (serial peripheral interface) ports, the IDP
(input data port), the parallel data acquisition port (PDAP), or
the UART.
Up to 67 channels of DMA are available on the ADSP-21469
processors as shown in Table 7. Programs can be downloaded to
the ADSP-21469 using DMA transfers. Other DMA features
include interrupt generation upon completion of DMA trans-
fers, and DMA chaining for automatic linked DMA transfers.
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| ADSP-21469KBCZ-4 | 功能描述:IC DSP 32/40BIT 450MHZ 324BGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP21469KBCZENG | 制造商:Analog Devices 功能描述: |
| ADSP-21469KBCZ-ENG | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBCZ-X | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBZ-EN | 制造商:Analog Devices 功能描述: |
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