參數(shù)資料
型號(hào)： ADSP-21469KBCZ-3
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 67/72頁(yè)
文件大小： 0K
描述： IC DSP 32/40BIT 400MHZ 324BGA
產(chǎn)品變化通告： Pin Function Change 08/Mar/2012
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類(lèi)型： 浮點(diǎn)
接口： DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： 外部
芯片上RAM： 5Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.05V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 324-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 324-CSPBGA
包裝： 托盤(pán)
ADSP-21469
Rev. 0
|
Page 7 of 72
|
June 2010
FAMILY PERIPHERAL ARCHITECTURE
The ADSP-21469 family contains a rich set of peripherals that
support a wide variety of applications including high quality
audio, medical imaging, communications, military, test equip-
ment, 3D graphics, speech recognition, motor control, imaging,
and other applications.
External Port
The external port interface supports access to the external mem-
ory through core and DMA accesses. The external memory
address space is divided into four banks. Any bank can be pro-
grammed as either asynchronous or synchronous memory. The
external ports are comprised of the following modules.
An Asynchronous Memory Interface which communicates
with SRAM, Flash, and other devices that meet the stan-
dard asynchronous SRAM access protocol. The AMI
supports 2M words of external memory in bank 0 and 4M
words of external memory in bank 1, bank 2, and bank 3.
A DDR2 DRAM controller. External memory devices up to
2 Gbits in size can be supported.
Arbitration Logic to coordinate core and DMA transfers
between internal and external memory over the external
port.
External Memory
The external port on the processor provides a high perfor-
mance, glueless interface to a wide variety of industry-standard
memory devices. The external port may be used to interface to
synchronous and/or asynchronous memory devices through the
use of its separate internal DDR2 memory controller. The 16-bit
DDR2 DRAM controller connects to industry-standard syn-
chronous DRAM devices, while the second 8-bit asynchronous
memory controller is intended to interface to a variety of mem-
ory devices. Four memory select pins enable up to four separate
devices to coexist, supporting any desired combination of syn-
chronous and asynchronous device types. Non-DDR2 DRAM
external memory address space is shown in Table 4.
SIMD Access to External Memory
The DDR2 controller on the ADSP-21469 processor supports
SIMD access on the 64-bit EPD (external port data bus) which
allows to access the complementary registers on the PEy unit in
the normal word space (NW). This improves performance since
there is no need to explicitly load the complimentary registers as
in SISD mode.
VISA and ISA Access to External Memory
The DDR2 controller on the ADSP-21469 processor supports
VISA code operation which reduces the memory load since the
VISA instructions are compressed. Moreover, bus fetching is
reduced because, in the best case, one 48-bit fetch contains three
valid instructions. Code execution from the traditional ISA
operation is also supported. Note that code execution is only
supported from bank 0 regardless of VISA/ISA. Table 5 shows
the address ranges for instruction fetch in each mode.
DDR2 Support
The ADSP-21469 supports a 16-bit DDR2 interface operating at
a maximum frequency of half the core clock. Execution from
external memory is supported. External memory devices up to
2 Gbits in size can be supported.
DDR2 DRAM Controller
The DDR2 DRAM controller provides a 16-bit interface to up to
four separate banks of industry-standard DDR2 DRAM devices.
Fully compliant with the DDR2 DRAM standard, each bank can
have its own memory select line (DDR2_CS3 – DDR2_CS0),
and can be configured to contain between 32M bytes and
256M bytes of memory. DDR2 DRAM external memory
address space is shown in Table 6.
A set of programmable timing parameters is available to config-
ure the DDR2 DRAM banks to support memory devices.
Note that the external memory bank addresses shown are for
normal-word (32-bit) accesses. If 48-bit instructions, as well as
32-bit data, are both placed in the same external memory bank,
care must be taken while mapping them to avoid overlap.
Asynchronous Memory Controller
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif-
ferent timing parameters, enabling connection to a wide variety
Table 4. External Memory for Non-DDR2 DRAM Addresses
Bank
Size in
Words
Address Range
Bank 0
2M
0x0020 0000 – 0x003F FFFF
Bank 1
4M
0x0400 0000 – 0x043F FFFF
Bank 2
4M
0x0800 0000 – 0x083F FFFF
Bank 3
4M
0x0C00 0000 – 0x0C3F FFFF
Table 5. External Bank 0 Instruction Fetch
Access Type
Size in
Words
Address Range
ISA (NW)
4M
0x0020 0000 - 0x005F FFFF
VISA (SW)
10M
0x0060 0000 – 0x00FF FFFF
Table 6. External Memory for DDR2 DRAM Addresses
Bank
Size in
Words
Address Range
Bank 0
62M
0x0020 0000 – 0x03FF FFFF
Bank 1
64M
0x0400 0000 – 0x07FF FFFF
Bank 2
64M
0x0800 0000 – 0x0BFF FFFF
Bank 3
64M
0x0C00 0000 – 0x0FFF FFFF
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