參數(shù)資料
型號(hào): AM188ER-25KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: CA-BAYONET
中文描述: 16-BIT, 25 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 68/112頁
文件大?。?/td> 2878K
代理商: AM188ER-25KCW
68
Am186
TM
ER and Am188
TM
ER Microcontrollers Data Sheet
DRAFT
t
CLCH
43
CLKOUTA Low Time
t
CLCK
37
X1 Low Time
t
CLCL
42
CLKOUTA Period
t
CLCLX
80
LCS Inactive Delay
t
CLCSL
81
LCS Active Delay
t
CLCSV
16
MCS/PCS Active Delay
t
CLDOX
30
Data Hold Time
t
CLDV
7
Data Valid Delay
Alphabetical Key to Switching Parameter Symbols
Notes:
The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76.
Parameter
Symbol
t
ARYCH
t
ARYCHL
t
ARYLCL
t
AVBL
t
AVCH
t
AVLL
t
AVRL
t
AVWL
t
AZRL
t
CH1CH2
t
CHAV
t
CHCK
t
CHCL
t
CHCSV
t
CHCSX
t
CHCTV
t
CHCV
t
CHCZ
t
CHDX
t
CHLH
t
CHLL
t
CHRFD
t
CHSV
t
CICOA
t
CICOB
t
CKHL
t
CKIN
t
CKLH
t
CL2CL1
t
CLARX
t
CLAV
t
CLAX
t
CLAZ
No.
49
51
52
87
14
12
66
65
24
45
68
38
44
67
18
22
64
63
8
9
11
79
3
69
70
39
36
40
46
50
5
6
15
Description
ARDY Resolution Transition Setup Time
ARDY Inactive Holding Time
ARDY Setup Time
A Address Valid to WHB, WLB Low
AD Address Valid to Clock High
AD Address Valid to ALE Low
A Address Valid to RD Low
A Address Valid to WR Low
AD Address Float to RD Active
CLKOUTA Rise Time
CLKOUTA High to A Address Valid
X1 High Time
CLKOUTA High Time
CLKOUTA High to LCS/UCS Valid
MCS/PCS Inactive Delay
Control Active Delay 2
Command Lines Valid Delay (after Float)
Command Lines Float Delay
Status Hold Time
ALE Active Delay
ALE Inactive Delay
CLKOUTA High to RFSH Valid
Status Active Delay
X1 to CLKOUTA Skew
X1 to CLKOUTB Skew
X1 Fall Time
X1 Period
X1 Rise Time
CLKOUTA Fall Time
ARDY Active Hold Time
AD Address Valid Delay
Address Hold
AD Address Float Delay
Parameter
Symbol
t
CLDX
t
CLEV
t
CLHAV
t
CLRF
t
CLRH
t
CLRL
t
CLSH
t
CLSL
CLSRY
t
CLTMV
t
COAOB
t
CVCTV
t
CVCTX
t
CVDEX
t
CXCSX
t
DVCL
t
DVSH
t
DXDL
t
HVCL
t
INVCH
t
INVCL
t
LCRF
t
LHAV
t
LHLL
t
LLAX
t
LOCK
t
LRLL
t
RESIN
t
RFCY
t
RHAV
t
RHDX
t
RHLH
t
RLRH
t
SHDX
t
SLDV
t
SRYCL
t
WHDEX
t
WHDX
t
WHLH
t
WLWH
No.
2
71
62
82
27
25
4
72
48
55
83
20
31
21
17
1
75
19
58
53
54
86
23
10
13
61
84
57
85
29
59
28
26
77
78
47
35
34
33
32
Description
Data in Hold
CLKOUTA Low to SDEN Valid
HLDA Valid Delay
CLKOUTA High to RFSH Invalid
RD Inactive Delay
RD Active Delay
Status Inactive Delay
CLKOUTA Low to SCLK Low
SRDY Transition Hold Time
Timer Output Delay
CLKOUTA to CLKOUTB Skew
Control Active Delay 1
Control Inactive Delay
DEN Inactive Delay
MCS/PCS Hold from Command Inactive
Data in Setup
Data Valid to SCLK High
DEN Inactive to DT/R Low
HOLD Setup
Peripheral Setup Time
DRQ Setup Time
LCS Inactive to RFSH Active Delay
ALE High to Address Valid
ALE Width
AD Address Hold from ALE Inactive
Maximum PLL Lock Time
LCS Precharge Pulse Width
RES Setup Time
RFSH Cycle Time
RD Inactive to AD Address Active
RD High to Data Hold on AD Bus
RD Inactive to ALE High
RD Pulse Width
SCLK High to SPI Data Hold
SCLK Low to SPI Data Valid
SRDY Transition Setup Time
WR Inactive to DEN Inactive
Data Hold after WR
WR Inactive to ALE High
WR Pulse Width
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