參數(shù)資料
型號(hào)： AM188ER-25KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： CA-BAYONET
中文描述： 16-BIT, 25 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 70/112頁(yè)
文件大?。?/td> 2878K
代理商： AM188ER-25KCW
70
Am186
TM
ER and Am188
TM
ER Microcontrollers Data Sheet
DRAFT
66
t
AVRL
A Address Valid to RD Low
2t
CLCL
–15=65
67
t
CHCSV
CLKOUTA High to LCS/UCS Valid
68
t
CHAV
CLKOUTA High to A Address Valid
Switching Characteristics over Commercial and Industrial Operating Ranges
Read Cycle (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
c
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Preliminary
Parameter
Description
25 MHz
Min
33 MHz
Min
No.
General Timing Requirements
1
t
DVCL
2
t
CLDX
General Timing Responses
3
t
CHSV
4
t
CLSH
CLAV
7
t
CLDV
8
t
CHDX
9
t
CHLH
10
t
LHLL
11
t
CHLL
12
t
AVLL
13
t
LLAX
14
t
AVCH
15
t
CLAZ
16
t
CLCSV
Symbol
Max
Max
Unit
Data in Setup
Data in Hold
(c)
10
3
8
3
ns
ns
Status Active Delay
Status Inactive Delay
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
ALE Inactive Delay
AD Address Valid to ALE Low
(a)
AD Address Hold from ALE Inactive
(a)
AD Address Valid to Clock High
AD Address Float Delay
MCS/PCS Active Delay
MCS/PCS Hold from Command
Inactive
(a)
MCS/PCS Inactive Delay
DEN Inactive to DT/R Low
(a)
Control Active Delay 1
(b)
DEN Inactive Delay
Control Active Delay 2
(b)
ALE High to Address Valid
0
0
0
0
20
20
20
0
0
0
0
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
15
t
CLCL
–10=30
t
CLCL
–10=20
20
15
t
CLCH
t
CHCL
0
t
CLAX
=0
0
t
CLCH
t
CHCL
0
t
CLAX
=0
0
20
20
15
15
17
t
CXCSX
t
CLCH
t
CLCH
ns
18
19
20
21
22
23
t
CHCSX
t
DXDL
t
CVCTV
t
CVDEX
t
CHCTV
t
LHAV
0
0
0
0
0
20
0
0
0
0
0
15
ns
ns
ns
ns
ns
ns
20
20
20
15
15
15
15
10
Read Cycle Timing Responses
24
t
AZRL
25
t
CLRL
26
t
RLRH
27
t
CLRH
28
t
RHLH
29
t
RHAV
59
t
RHDX
AD Address Float to RD Active
RD Active Delay
RD Pulse Width
RD Inactive Delay
RD Inactive to ALE High
(a)
RD Inactive to AD Address Active
(a)
RD High to Data Hold on AD Bus
(c)
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
15
2t
CLCL
–15=65
0
t
CLCH
–3
t
CLCL
–10=30
0
2t
CLCL
–15=45
0
t
CLCH
–3
t
CLCL
–10=20
0
2t
CLCL
–15=45
0
0
20
15
0
0
20
20
15
15
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參數(shù)描述
AM188ER-25KI/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor
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