參數(shù)資料
型號(hào): AM188ER-25KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類(lèi): 微控制器/微處理器
英文描述: CA-BAYONET
中文描述: 16-BIT, 25 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 78/112頁(yè)
文件大?。?/td> 2878K
代理商: AM188ER-25KCW
78
Am186
TM
ER and Am188
TM
ER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Read Cycle (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Preliminary
Parameter
Description
25 MHz
Min
33 MHz
Min
No.
General Timing Requirements
1
t
DVCL
2
t
CLDX
General Timing Responses
5
t
CLAV
7
t
8
t
CHDX
9
t
CHLH
10
t
LHLL
11
t
CHLL
23
t
LHAV
80
t
CLCLX
81
t
CLCSL
84
t
LRLL
Read Cycle Timing Responses
24
t
AZRL
25
t
CLRL
26
t
RLRH
27
t
CLRH
28
t
RHLH
59
t
RHDX
66
t
AVRL
68
t
CHAV
Symbol
Max
Max
Unit
Data in Setup
Data in Hold
(b)
10
3
8
3
ns
ns
AD Address Valid Delay
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
ALE Inactive Delay
ALE High to Address Valid
LCS Inactive Delay
LCS Active Delay
LCS Precharge Pulse Width
0
0
0
20
20
0
0
0
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
15
t
CLCL
–10=30
t
CLCL
–10=20
20
15
15
0
0
10
0
0
20
20
15
15
t
CLCL
+ t
CLCH
–3
t
CLCL
+ t
CLCH
–3
AD Address Float to RD Active
RD Active Delay
RD Pulse Width
RD Inactive Delay
RD Inactive to ALE High
(a)
RD High to Data Hold on AD Bus
(b)
A Address Valid to RD Low
CLKOUTA High to A Address Valid
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
20
15
2t
CLCL
–15=65
0
t
CLCH
–3
0
2t
CLCL
–15=65
0
2t
CLCL
–15=45
0
t
CLCH
–3
0
2t
CLCL
–15=45
0
20
15
20
15
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