參數(shù)資料
型號(hào)： AM188ER-25KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： CA-BAYONET
中文描述： 16-BIT, 25 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 82/112頁(yè)
文件大?。?/td> 2878K
代理商： AM188ER-25KCW
82
Am186
TM
ER and Am188
TM
ER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, WR, WHB and WLB signals.
Preliminary
Parameter
Description
40 MHz
Min
50 MHz
Min
No.
General Timing Responses
5
t
CLAV
7
t
CLDV
8
t
CHDX
9
t
CHLH
t
11
t
CHLL
20
t
CVCTV
23
t
LHAV
80
t
CLCLX
81
t
CLCSL
84
t
LRLL
Write Cycle Timing Responses
30
t
CLDOX
31
t
CVCTX
32
t
WLWH
33
t
WHLH
34
t
WHDX
65
t
AVWL
68
t
CHAV
87
t
AVBL
Symbol
Max
Max
Unit
AD Address Valid Delay
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Inactive Delay
Control Active Delay 1
(b)
ALE High to Address Valid
LCS Inactive Delay
LCS Active Delay
LCS Precharge Pulse Width
0
0
0
12
12
0
0
0
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
10
t
–5=20
12
12
10
10
0
0
5
0
0
7.5
0
0
12
12
10
10
t
CLCL
+ t
CLCH
–1.25
t
CLCL
+ t
CLCH
–1
Data Hold Time
Control Inactive Delay
(b)
WR Pulse Width
WR Inactive to ALE High
(a)
Data Hold after WR
(a)
A Address Valid to WR Low
CLKOUTA High to A Address Valid
A Address Valid to WHB, WLB Low
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
12
10
2t
CLCL
–10=40
t
CLCH
–2
t
CLCL
–10=15
t
CLCL
+t
CHCL
–1.25
0
t
CHCL
–1.25
35
t
CLCH
–2
12
t
CLCL
+t
CHCL
–1.25
0
t
CHCL
–1.25
10
18
10
15
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參數(shù)描述
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