參數(shù)資料
型號(hào): AM188ER-25KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: CA-BAYONET
中文描述: 16-BIT, 25 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 81/112頁
文件大?。?/td> 2878K
代理商: AM188ER-25KCW
Am186
TM
ER and Am188
TM
ER Microcontrollers Data Sheet
81
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, WR, WHB and WLB signals.
Preliminary
Parameter
25 MHz
Min
33 MHz
Min
No.
General Timing Responses
5
t
CLAV
7
t
CLDV
8
t
CHDX
9
t
CHLH
t
11
t
CHLL
23
t
LHAV
20
t
CVCTV
80
t
CLCLX
81
t
CLCSL
84
t
LRLL
Write Cycle Timing Responses
30
t
CLDOX
31
t
CVCTX
32
t
WLWH
33
t
WHLH
34
t
WHDX
65
t
AVWL
Symbol Description
Max
Max
Unit
AD Address Valid Delay
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Inactive Delay
ALE High to Address Valid
Control Active Delay 1
(b)
LCS Inactive Delay
LCS Active Delay
LCS Precharge Pulse Width
0
0
0
20
20
0
0
0
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
15
t
–10=30
t
–10=20
20
15
15
15
0
0
0
0
10
0
0
20
20
20
15
15
t
CLCL
+ t
CLCH
–3
t
CLCL
+ t
CLCH
–3
Data Hold Time
Control Inactive Delay
(b)
WR Pulse Width
WR Inactive to ALE High
(a)
Data Hold after WR
(a)
A Address Valid to WR Low
CLKOUTA High to A
Address Valid
A Address Valid to WHB, WLB
Low
0
0
0
0
ns
ns
ns
ns
ns
ns
20
15
2t
CLCL
–10=70
t
CLCH
–2
t
CLCL
–10=30
t
CLCL
+t
CHCL
–3
2t
CLCL
–10=50
t
CLCH
–2
t
CLCL
–10=20
t
CLCL
+t
CHCL
–3
68
t
CHAV
0
20
0
15
ns
87
t
AVBL
t
CHCL
–3
20
t
CHCL
–3
15
ns
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