參數(shù)資料
型號(hào)： AM188ER-25KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： CA-BAYONET
中文描述： 16-BIT, 25 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 73/112頁(yè)
文件大小： 2878K
代理商： AM188ER-25KCW
Am186
TM
ER and Am188
TM
ER Microcontrollers Data Sheet
73
DRAFT
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
Switching Characteristics over Commercial and Industrial Operating Ranges
Write Cycle (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
Preliminary
Parameter
25 MHz
Min
33 MHz
Min
No.
General Timing Responses
3
t
CHSV
4
t
CLSH
5
t
CLAV
7
t
CLDV
8
t
CHDX
CHLH
10
t
LHLL
11
t
CHLL
12
t
AVLL
13
t
LLAX
14
t
AVCH
16
t
CLCSV
Symbol Description
Max
Max
Unit
Status Active Delay
Status Inactive Delay
AD Address Valid Delay
Data Valid Delay
Status Hold Time
ALE Width
ALE Inactive Delay
AD Address Valid to ALE Low
(a)
AD Address Hold from ALE Inactive
(a)
AD Address Valid to Clock High
MCS/PCS Active Delay
MCS/PCS Hold from Command
Inactive
(a)
MCS/PCS Inactive Delay
DEN Inactive to DT/R Low
(a)
Control Active Delay 1
(b)
ALE High to Address Valid
Write Cycle Timing Responses
30
t
CLDOX
Data Hold Time
31
t
CVCTX
32
t
WLWH
WR Pulse Width
33
t
WHLH
34
t
WHDX
35
t
WHDEX
65
t
AVWL
A Address Valid to WR Low
67
t
CHCSV
CLKOUTA High to LCS/UCS Valid
68
t
CHAV
CLKOUTA High to A Address Valid
87
t
AVBL
A Address Valid to WHB, WLB Low
0
0
0
0
0
20
20
20
20
0
0
0
0
0
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CLCL
–10=30
t
CLCL
–10=20
20
15
t
CLCH
t
CHCL
0
0
t
CLCH
t
CHCL
0
0
20
15
17
t
CXCSX
t
CLCH
t
CLCH
ns
18
19
20
23
t
CHCSX
t
DXDL
t
CVCTV
t
LHAV
0
0
0
20
0
0
0
10
15
ns
ns
ns
ns
20
15
15
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Inactive Delay
(b)
20
15
2t
CLCL
–10=70
t
CLCH
–2
t
CLCL
–10=30
t
CLCH
–3
t
CLCL
+t
CHCL
–3
0
0
t
CHCL
–3
2t
CLCL
–10=50
t
CLCH
–2
t
CLCL
–10=20
t
CLCH
–5
t
CLCL
+t
CHCL
–3
0
0
t
CHCL
–3
WR Inactive to ALE High
(a)
Data Hold after WR
(a)
WR Inactive to DEN Inactive
(a)
20
20
20
15
15
15
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