AMD
P R E L I M I N A R Y
104
Am79C970A
Table 19. I/O Map In Word I/O Mode (DWIO = 0)
Offset
No. of Bytes
Register
00h – 0Fh
16
APROM
10h
2
RDP
12h
2
RAP (shared by RDP
and BDP)
14h
2
Reset Register
16h
2
BDP
18h – 1Fh
8
Reserved
All I/O resources must be accessed in word quantities
and on word addresses. The Address PROM locations
can also be read in byte quantities. The only allowed
DWord operation is a write access to the RDP,
which switches the device to DWord I/O mode. A read
access other than listed in the table below will yield
undefined data, a write operation may cause unex-
pected reprogramming of the PCnet-PCI II controller
control registers.
Table 20. Legal I/O Accesses in Word I/O Mode (DWIO = 0)
AD[4:0]
BE
[3:0]
Type
Comment
0XX00
1110
RD
Byte Read of APROM Location 0h, 4h, 8h or Ch
0XX01
1101
RD
Byte Read of APROM Location 1h, 5h, 9h or Dh
0XX10
1011
RD
Byte Read of APROM Location 2h, 6h, Ah or Eh
0XX11
0111
RD
Byte Read of APROM Location 3h, 7h, Bh or Fh
0XX00
1100
RD
Word Read of APROM Locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h
and 9h or Ch and Dh
0XX10
0011
RD
Word Read of APROM Locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh
and Ah or Fh and Eh
10000
1100
RD
Word Read of RDP
10010
0011
RD
Word Read of RAP
10100
1100
RD
Word Read of Reset Register
10110
0011
RD
Word Read of BDP
0XX00
1100
WR
Word Write to APROM Locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h
and 9h or Ch and Dh
0XX10
0011
WR
Word Write to APROM Locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh
and Ah or Fh and Eh
10000
1100
WR
Word Write to RDP
10010
0011
WR
Word Write to RAP
10100
1100
WR
Word Write to Reset Register
10110
0011
WR
Word Write to BDP
10000
0000
WR
DWord Write to RDP, switches Device to DWord I/O Mode
Double Word I/O Mode
The PCnet-PCI II controller can be configured to oper-
ate in DWord (32bit) I/O mode. The software can invoke
the DWIO mode by performing a DWord write access to
the I/O location at offset 10h (RDP). The data of the write
access must be such that it does not affect the intended
operation of the PCnet-PCI II controller. Setting the de-
vice into 32-bit I/O mode is usually the first operation af-
ter H_RESET or S_RESET. The RAP register will point
to CSR0 at that time. Writing a value of ZERO to CSR0
is a save operation. DWIO (BCR18, bit 7) will be set to
ONE as indicating that the PCnet-PCI II controller oper-
ates in 32-bit I/O mode.
Note that even though the I/O resource mapping
changes when the I/O mode setting changes, the RDP
location offset is the same for both modes. Once the
DWIO bit has been set to ONE, only H_RESET or
S_RESET can clear it to ZERO. The DWIO mode set-
ting is unaffected by setting the STOP bit.
The table below shows how the 32 bytes of address
space are used in DWord I/O mode.