參數(shù)資料
型號(hào)： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁(yè)數(shù)： 120/219頁(yè)
文件大?。?/td> 1065K
代理商： AM79C970A
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AMD
P R E L I M I N A R Y
120
Am79C970A
Read/Write accessible always.
TXSTRTM is set to ONE by
H_RESET or S_RESET and is
unaffected
by
STOP bit.
Jabber Error is set by the PCnet-
PCI II controller when the T-MAU
exceeds the allowed transmis-
sion time limit. Jabber can only
be asserted in 10BASE-T mode.
When JAB is set,
INTA
is as-
serted if IENA is ONE and the
mask bit JABM is ZERO.
Read/Write accessible always.
JAB is cleared by the host by writ-
ing a ONE. Writing a ZERO has
no effect. JAB is cleared by
H_RESET, S_RESET or by set-
ting the STOP bit.
When the value 01h has been
programmed into the SWSTYLE
register (BCR20, bits 7–0) for
ILACC (Am79C900) compatibil-
ity, then this bit has no meaning
and PCnet-PCI II controller will
never set the value of this bit
to ONE.
Jabber Error Mask. If JABM is
set, the JAB bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
JABM is set to ONE by
H_RESET or S_RESET and
is unaffected by setting the
STOP bit.
When the value 01h has been
programmed into the SWSTYLE
register (BCR20, bits 7–0) for
ILACC (Am79C900) compatibil-
ity, then this bit has no meaning
and PCnet-PCI II controller will
clear the value of this bit
to ZERO.
setting
the
1
JAB
0
JABM
CSR5: Extended Control and Interrupt
Bit
Name
Description
Certain bits in CSR5 indicate the
cause of an interrupt. The regis-
ter is designed so that these indi-
cator bits are cleared by writing
ONEs to those bit locations. This
means that the software can read
CSR5 and write back the
value just read to clear the
interrupt condition.
Reserved locations. Written as
ZEROs and read as undefined.
31–16
RES
15
TOKINTD
Transmit OK Interrupt Disable. If
TOKINTD is set to ONE, the
TINT bit in CSR0 will not be set
when a transmission was suc-
cessful. Only a transmit error will
set the TINT bit.
TOKINTD has no effect when
LTINTEN (CSR5, bit 14) is set to
ONE. A transmit descriptor with
LTINT set to ONE will always
cause TINT to be set to ONE, in-
dependent of the success of
the transmission.
Read/Write accessible always.
TOKINTD
is
H_RESET or S_RESET and
is unaffected by setting the
STOP bit.
Last Transmit Interrupt Enable.
When set to ONE, the LTINTEN
bit will cause the PCnet-PCI II
controller to read bit 28 of TMD1
as LTINT. The setting LTINT will
determine if TINT will be set at
the end of the transmission.
Read/Write accessible always.
LTINTEN
is
H_RESET or S_RESET and
is unaffected by setting the
STOP bit.
Reserved locations. Written as
ZEROs and read as undefined.
System Interrupt is set by the
PCnet-PCI II controller when it
detects a system error during a
bus master transfer on the PCI
bus. System errors are data par-
ity error, master abort or a target
abort. The setting of SINT due to
a data parity error is not depend-
ent on the setting of PERREN
(PCI Command register, bit 6).
When SINT is set,
INTA
is as-
serted if the enable bit SINTE is
ONE. Note that the assertion of
an interrupt due to SINT is not de-
pendent on the state of the INEA
bit, since INEA is cleared by the
STOP reset generated by the
system error.
Read/Write accessible always.
SINT is cleared by the host by
writing a ONE. Writing a ZERO
has no effect. The state of SINT
is not affected by clearing any of
the PCI Status register bits that
get set when a data parity error
(DATAPERR, bit 8), master abort
(RMABORT, bit 13) or target
cleared
by
14
LTINTEN
cleared
by
13–12
RES
11
SINT
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