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參數(shù)資料
| 型號： | AM79C970A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品 |
| 文件頁數(shù)： | 88/219頁 |
| 文件大小： | 1065K |
| 代理商： | AM79C970A |
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AMD
P R E L I M I N A R Y
88
Am79C970A
Full-Duplex Operation
The PCnet-PCI II controller supports full-duplex opera-
tion on all three network interfaces: AUI, 10BASE-T, and
GPSI. full-duplex operation allows simultaneous trans-
mit and receive activity on the TXD
±
and RXD
±
pairs of
the 10BASE-T port, the DO
±
and DI
±
pairs of the AUI
port, or the TXDAT and RXDAT pins of the GPSI port.
Full-duplex operation is enabled by the FDEN and
AUIFD bits located in BCR9. When operating in full-du-
plex mode, the following changes to the device opera-
tion are made:
Bus Interface/Buffer Management Unit changes:
I
The first 64 bytes of every transmit frame are not pre-
served in the transmit FIFO during transmission of
the first 512 bits as described in the section “Trans-
mit Exception Conditions”. Instead, when full-duplex
mode is active and a frame is being transmitted, the
XMTFW bits (CSR80, bits 9–8) always
govern when
transmit DMA is requested.
I
Successful reception of the first 64 bytes of every re-
ceive frame is not a requirement for receive DMA to
begin as described in the section “Receive Excep-
tion Condition”. Instead, receive DMA will be re-
quested as soon as either the Receive FIFO
Watermark (CSR80, bits 13–12) is reached or a
complete valid receive frame is detected, regardless
of length. This receive FIFO operation is identical to
when the RPA bit (CSR124, bit 3) is set during half-
duplex mode operation.
MAC Engine changes:
I
Changes to the Transmit Deferral mechanism:
– Transmission is not deferred while receive is
active.
– The Inter Packet Gap (IPG) counter which gov-
erns transmit deferral during the IPG between
back-to-back transmits is started when transmit
activity for the first packet ends instead of when
transmit and carrier activity ends.
I
When the AUI or GPSI port is active, Loss of Carrier
(LCAR) reporting is disabled. (LCAR is still reported
when the 10BASE-T port is active if a packet is trans-
mitted while in Link Fail state.)
I
The 4.0
μ
s carrier sense blinding period after a trans-
mission during which the SQE test normally occurs is
disabled.
I
When the AUI or GPSI port is active, the SQE Test
error reporting (CERR) is disabled. (CERR is still re-
ported when the 10BASE-T port is active if a packet
is transmitted while in Link Fail state.)
I
The collision indication input to the MAC engine is
ignored.
T-MAU changes:
I
The internal transmit to receive feedback path which
is used to indicate carrier sense during normal trans-
mission in half-duplex mode is disabled.
I
The collision detect circuit is disabled.
I
The SQE test function is disabled.
Full-Duplex Link Status LED Support
The PCnet-PCI II controller provides a bit in each of the
LED Status registers (BCR4, BCR5, BCR6, BCR7) to
display the Full-Duplex Link Status. If the FDLSE bit
(bit 8) is set, a value of ONE will be sent to the associ-
ated LEDOUT bit when the T-MAU is in the Full-Duplex
Link Pass state.
General Purpose Serial Interface
The General Purpose Serial Interface (GPSI) provides a
direct interface to the MAC section of the PCnet-PCI II
controller. All signals are digital and data is non-en-
coded. The GPSI allows use of an external Manchester
encoder/decoder such as the Am7992B Serial Interface
Adapter (SIA). In addition, it allows the PCnet-PCI II
controller to be used as a MAC sublayer engine in a re-
peater designs based on the Am79C981 IMR+.
GPSI mode is invoked by setting the GPSIEN bit
(CSR124, bit 4) to ONE and by selecting the interface
through the PORTSEL bits of the Mode register
(CSR15, bits 8–7).
The GPSI interface uses some of the same pins as the
interface to the Expansion ROM. Simultaneous use of
both functions is not possible. Reading from the Expan-
sion ROM and then reconfiguring the pins to the GPSI
mode is supported. With this approach an external
transceiver is required to prevent contention between
the GPSI signals and the data outputs from the Expan-
sion ROM.
EROE
can be used as control signal for the
external transceiver.
After an H_RESET all pins are internally configured to
function as Expansion ROM interface. When the GPSI
interface is selected by setting PORTSEL (CSR15, bits
8–7) to 10b, the PCnet-PCI II controller will terminate all
further read accesses to Expansion ROM by asserting
TRDY
within two clock cycles. The read data will
be undefined.
During the boot procedure the system will try to find an
Expansion ROM. A PCI system assumes that an Expan-
sion ROM is present when it reads the ROM signature
55h (byte 0) and AAh (byte 1). A design without Expan-
sion ROM can guarantee that the Expansion ROM de-
tection fails by connecting two adjacent ERD pins
together. The recommended pins are pin 77
(ERD6/TXEN) and pin 78 (ERD5), since TXEN should
have an external pull-down.
GPSI signal functions are described in the pin descrip-
tion section under the GPSI subheading.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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