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參數(shù)資料
| 型號： | AM79C970A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品 |
| 文件頁數(shù)： | 78/219頁 |
| 文件大?。?/td> | 1065K |
| 代理商： | AM79C970A |
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AMD
P R E L I M I N A R Y
78
Am79C970A
When a unicast frame arrives at the PCnet-PCI II con-
troller, the controller will accept the frame if the destina-
tion address field of the incoming frame exactly matches
the 6-byte station address stored in the Physical Ad-
dress registers (PADR, CSR12 to CSR14). The byte or-
dering is such that the first byte received from the
network (after the SFD) must match the least significant
byte of CSR12 (PADR[7:0]), and the sixth byte received
must match the most significant byte of CSR14
(PADR[47:40]).
When DRCVPA (CSR15, bit 13) is set to ONE, the
PCnet-PCI II controller will not accept unicast frames.
If the incoming frame is multicast, the PCnet-PCI II con-
troller performs a calculation on the contents of the
destination address field to determine whether or not to
accept the frame. This calculation is explained in
the section that describes the Logical Address
Filter (LADRF).
When all bits of the LADRF registers are 0, no multicast
frames are accepted, except for broadcast frames.
Although broadcast frames are classified as special
multicast frames, they are treated differently by the
PCnet-PCI II controller hardware. Broadcast frames are
always accepted, except when DRCVBC (CSR15, bit
14) is set.
None of the address filtering described above applies
when the PCnet-PCI II controller is operating in the pro-
miscuous mode. In the promiscuous mode, all properly
formed packets are received, regardless of the contents
of their destination address fields. The promiscuous
mode overrides the Disable Receive Broadcast bit
(DRCVBC bit l4 in the MODE register) and the Disable
Receive Physical Address bit (DRCVPA, CSR15,
bit 13).
The PCnet-PCI II controller operates in promiscuous
mode when PROM (CSR15, bit 15) is set.
In addition, the PCnet-PCI II controller provides the Ex-
ternal Address Detection Interface (EADI) to allow
external address filtering. See the section “External Ad-
dress Detection Interface” for further detail.
The receive descriptor entry RMD1 contains three bits
that indicate which method of address matching caused
the PCnet-PCI II controller to accept the frame. Note
that these indicator bits are only available when the
PCnet-PCI II controller is programmed to use 32-bit
structures for the descriptor entries (BCR20, bit 7–0,
SWSTYLE is set to ONE, TWO or THREE).
PAM (RMD1, bit 22) is set by the PCnet-PCI II controller
when it accepted the received frame due to a match of
the frame’s destination address with the content of the
physical address register.
LAFM (RMD1, bit 21) is set by the PCnet-PCI II control-
ler when it accepted the received frame based on the
value in the logical address filter register.
BAM (RMD1, bit 20) is set by the PCnet-PCI II controller
when it accepted the received frame because the
frame’s destination address is of the type “Broadcast”.
If DRCVBC (CSR15, bit 14) is cleared to ZERO, only
BAM, but not LAFM will be set when a Broadcast frame
is received, even if the Logical Address Filter is pro-
grammed in such a way that a Broadcast frame would
pass the hash filter. If DRCVBC is set to ONE and the
Logical Address Filter is programmed in such a way that
a Broadcast frame would pass the hash filter, LAFM will
be set on the reception of a Broadcast frame.
When the PCnet-PCI II controller operates in promiscu-
ous mode and none of the three match bits is set, it is an
indication that the PCnet-PCI II controller only accepted
the frame because it was in promiscuous mode.
When the PCnet-PCI II controller is not programmed to
be in promiscuous mode, but the EADI interface is en-
abled, then when none of the three match bits is set, it is
an indication that the PCnet-PCI II controller only ac-
cepted the frame because it was not rejected by driving
the
EAR
pin LOW within 64 bytes after SFD.
Table 6. Receive Address Match
PAM
LAFM
BAM
DRCVBC
Comment
0
0
0
X
Frame accepted due to PROM = 1 or no EADI reject
1
0
0
X
Physical Address Match
0
1
0
0
Logical Address Filter Match; Frame is not of Type Broadcast
0
1
0
1
Logical Address Filter Match; Frame can be of Type Broadcast
0
0
1
0
Broadcast Frame
Automatic Pad Stripping
During reception of an 802.3 frame the pad field can be
stripped automatically. Setting ASTRP_RCV (CSR4, bit
0) to ONE enables the automatic pad stripping feature.
The pad field will be stripped before the frame is passed
to the FIFO, thus preserving FIFO space for additional
frames. The FCS field will also be stripped, since it is
computed at the transmitting station based on the data
and pad field characters, and will be invalid for a receive
frame that has had the pad characters stripped.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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