P R E L I M I N A R Y
AMD
95
Am79C970A
EEPROM MAP
The automatic EEPROM read operation will access 18
words (i.e. 36 bytes) of the EEPROM. The format of the
EEPROM contents is shown below, beginning with the
byte that resides at the lowest EEPROM address:
Table 12. EEPROM Content
Word
Address
Byte
Addr.
Byte
Addr.
Most Significant Byte
Least Significant Byte
00h
01h
Second byte of the ISO 8802-3
(IEEE/ANSI 802.3) station physical
address for this node
00h
First byte of the ISO 8802-3
(IEEE/ANSI 802.3) station physical
address for this node, where first byte
refers to the first byte to appear on
the 802.3 medium
(Lowest
EEPROM
address)
01h
03h
Fourth byte of the node address
02h
Third byte of the node address
02h
05h
Sixth byte of the node address
04h
Fifth byte of the node address
03h
07h
Reserved Location: must be 00h
06h
Reserved location must be 00h
04h
09h
Hardware ID: must be 11h if compatibility
to AMD drivers is desired
08h
Reserved location must be 00h
05h
0Bh
User programmable space
0Ah
User programmable space
06h
0Dh
MSByte of two-byte checksum, which is the
is the sum of bytes 00h–0Bh and bytes
0Eh and 0Fh
0Ch
LSByte of two-byte checksum, which
is the sum of bytes 00h–0Bh and bytes
0Eh and 0Fh
07h
0Fh
Must be ASCII W (57h) if compatibility to
AMD driver software is desired
0Eh
Must be ASCII W (57h) if compatibility to
AMD driver software is desired
08h
11h
BCR4[15:8] (Link Status LED)
10h
BCR4[7:0] (Link Status LED)
09h
13h
BCR5[15:8] (LED1 Status)
12h
BCR5[7:0] (LED1 Status)
0Ah
15h
BCR18[15:8] (Burst and Bus Control)
14h
BCR18[7:0] (Burst and Bus Control)
0Bh
17h
BCR2[15:8] (Miscellaneous Configuration)
16h
BCR2[7:0] (Miscellaneous Configuration)
0Ch
19h
BCR6[15:8] (LED2 Status)
18h
BCR6[7:0] (LED2 Status)
0Dh
1Bh
BCR7[15:8] (LED3 Status)
1Ah
BCR7[7:0] (LED3 Status)
0Eh
1Dh
BCR9[15:8] (Full-Duplex Control)
1Ch
BCR9[7:0] (Full-Duplex Control)
0Fh
1Fh
Checksum adjust byte for the first 36 bytes
of the EEPROM contents, checksum of the
first 36 bytes of the EEPROM should
total to FFh
1Eh
Reserved location must be 00h
10h
21h
BCR22[15:8] (PCI Latency)
20h
BCR22[7:0] (PCI Latency)
11h
23h
Reserved location must be 00h
22h
Reserved location must be 00h
Note that the first bit out of any word location in the
EEPROM is treated as the MSB of the register that is be-
ing programmed. For example, the first bit out of
EEPROM word location 08h will be written into BCR4,
bit 15, the second bit out of EEPROM word location 08h
will be written into BCR4, bit 14, etc.
There are two checksum locations within the EEPROM.
The first checksum will be used by AMD driver software
to verify that the ISO 8802-3 (IEEE/ANSI 802.3) station
address has not been corrupted. The value of bytes 0Ch
and 0Dh should match the sum of bytes 00h through
0Bh and 0Eh and 0Fh. The second checksum location
— byte 21h — is not a checksum total, but is, instead, a
checksum adjustment. The value of this byte should be
such that the total checksum for the entire 36 bytes of
EEPROM data equals the value FFh. The checksum
adjust byte is needed by the PCnet-PCI II controller in
order to verify that the EEPROM content has not
been corrupted.
LED Support
The PCnet-PCI II controller can support up to four LEDs.
LED outputs
LNKST
,
LED1
and
LED2
allow for direct
connection of an LED and its supporting pullup device.
LED output
LED3
may require an additional buffer
between the PCnet-PCI II controller output pin and the
LED and its supporting pullup device.
Because the
LED3
output is multiplexed with other
PCnet-PCI II controller functions, it may not always be
possible to connect an LED circuit directly to the
LED3
pin. In applications that want to use the pin to drive an