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參數(shù)資料
| 型號： | AM79C970A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品 |
| 文件頁數(shù)： | 23/219頁 |
| 文件大?。?/td> | 1065K |
| 代理商： | AM79C970A |
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P R E L I M I N A R Y
AMD
23
Am79C970A
INTA
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: BABL, EXDINT, IDON,
JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT,
SINT, SLPINT, TINT, TXSTRT and UINT. Each status
flag has either a mask or an enable bit which allows for
suppression of
INTA
assertion. The flags have the
following meaning:
Input/Output
Table 1. Interrupt Flags
BABL
Babble
EXDINT
Excessive Deferral
IDON
Initialization Done
JAB
Jabber
MERR
Memory Error
MISS
Missed Frame
MFCO
Missed Frame Count Overflow
MPINT
Magic Packet Interrupt
RCVCCO
Receive Collision Count Overflow
RINT
Receive Interrupt
SLPINT
Sleep Interrupt
SINT
System Error
TINT
Transmit Interrupt
TXSTRT
Transmit Start
UINT
User Interrupt
By default
INTA
is an open-drain output. For applica-
tions that need a high-active edge sensitive interrupt
signal, the
INTA
pin can be configured for this mode by
setting INTLEVEL (BCR2, bit 7) to ONE.
When
RST
is active,
INTA
is an input for NAND
tree testing.
IRDY
Initiator Ready
IRDY
indicates the ability of the initiator of the transac-
tion to complete the current data phase.
IRDY
is used in
conjunction with
TRDY
. Wait states are inserted until
both
IRDY
and
TRDY
are asserted simultaneously. A
data phase is completed on any clock when both
IRDY
and
TRDY
are asserted.
Input/Output
When the PCnet-PCI II controller is a bus master, it as-
serts
IRDY
during all write data phases to indicated that
valid data is present on AD[31:0]. During all read data
phases the device asserts
IRDY
to indicate that it is
ready to accept the data.
When the PCnet-PCI II controller is the target of a trans-
action, it checks
IRDY
during all write data phases to de-
termine if valid data is present on AD[31:0]. During all
read data phases the device checks
IRDY
to determine
if the initiator is ready to accept the data.
When
RST
is active,
IRDY
is an input for NAND
tree testing.
LOCK
Lock
In slave mode,
LOCK
is an input to the PCnet-PCI II con-
troller. A bus master can lock the device to guarantee an
atomic operation that requires multiple transactions.
Input
The PCnet-PCI II controller will never assert
LOCK
as
a master.
When
RST
is active,
LOCK
is an input for NAND
tree testing.
PAR
Parity
Parity is even parity across AD[31:0] and C/
BE
[3:0].
When the PCnet-PCI II controller is a bus master, it gen-
erates parity during the address and write data phases.
It checks parity during read data phases. When the
PCnet-PCI II controller operates in slave mode, it
checks parity during every address phase. When it is the
target of a cycle, it checks parity during write data
phases and it generates parity during read data phases.
Input/Output
When
RST
is active, PAR is an input for NAND
tree testing.
PERR
Parity Error
During any slave write transaction and any master read
transaction, the PCnet-PCI II controller asserts
PERR
when it detects a data parity error and reporting of the
error is enabled by setting PERREN (PCI Command
register, bit 6) to ONE. During any master write transac-
tion the PCnet-PCI II controller monitors
PERR
to see if
the target reports a data parity error.
Input/Output
When
RST
is active,
PERR
is an input for NAND
tree testing.
REQ
Bus Request
The PCnet-PCI II controller asserts
REQ
pin as a signal
that it wishes to become a bus master.
REQ
is driven
high when the PCnet-PCI II controller does not
request the bus.
Input/Output
When
RST
is active,
REQ
is an input for NAND
tree testing.
RST
Reset
When
RST
is asserted low, then the PCnet-PCI II con-
troller performs an internal system reset of the type
Input
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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