參數(shù)資料
型號(hào)： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁(yè)數(shù)： 147/219頁(yè)
文件大?。?/td> 1065K
代理商： AM79C970A
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P R E L I M I N A R Y
AMD
147
Am79C970A
is passed to the LEDOUT signal
whenever full-duplex operation
on the AUI port is enabled
(both FDEN and AUIFD bits in
BCR9 are set to ONE). When the
GPSI port is active, a value of
ONE is passed to the LEDOUT
signal whenever full-duplex op-
eration on the GPSI port is en-
abled (FDEN bit in BCR9 is set
to ONE).
Read/Write accessible always.
FDLSE is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
7
PSE
Pulse Stretcher Enable. When
this bit is set to ONE, the LED illu-
mination time is extended so that
brief occurrences of the enabled
function will be seen on this LED
output. A value of ZERO disables
the pulse stretcher.
Read/Write accessible always.
PSE is set to ONE by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
6
LNKSTE
Link Status Enable. When this bit
is set to ONE, a value of ONE will
be passed to the LEDOUT bit in
this register when the T-MAU op-
erating in half-duplex mode is in
Link Pass state. When the
T-MAU operating in half-duplex
mode is in Link Fail state, a value
of ZERO is passed to the
LEDOUT bit.
The function of this bit is masked
if the 10BASE-T port is operating
in full-duplex mode. This allows a
system to have separate LEDs
for half-duplex Link Status and
for full-duplex Link Status.
Read/Write accessible always.
LNKSTE is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
5
RCVME
Receive Match Status Enable.
When this bit is set to ONE, a
value of ONE is passed to the
LEDOUT bit in this register
when the there is receive activity
on the network that has passed
the address match function
for this node. All address
matching modes are included:
physical, logical filtering, broad-
cast and promiscuous.
Read/Write accessible always.
RCVME is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
4
XMTE
Transmit Status Enable. When
this bit is set to ONE, a value of
ONE is passed to the LEDOUT
bit in this register when there is
transmit activity on the network.
Read/Write accessible always.
XMTE is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
3
RXPOLE
Receive Polarity Status Enable.
When this bit is set to ONE, a
value of ONE is passed to the
LEDOUT bit in this register when
the polarity of the RXD
±
pair is
not reversed.
Receive polarity indication is
valid only if the T-MAU is in link
pass state.
Read/Write accessible always.
RXPOLE
is
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
cleared
by
2
RCVE
Receive Status Enable. When
this bit is set to ONE, a value of
ONE is passed to the LEDOUT
bit in this register when there is
receive activity on the network.
Read/Write accessible always.
RCVE is set to ONE by
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
1
JABE
Jabber status Enable. When this
bit is set to ONE, a value of
ONE is passed to the LEDOUT
bit in this register when the
PCnet-PCI II controller is jabber-
ing on the network.
Read/Write accessible always.
JABE is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
0
COLE
Collision status Enable. When
this bit is set to ONE, a value of
ONE is passed to the LEDOUT
bit in this register when there is
collision activity on the network.
The activity on the collision
inputs to the AUI or GPSI ports
within the first 4
μ
s after every
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