參數(shù)資料
型號(hào)： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁(yè)數(shù)： 22/219頁(yè)
文件大小： 1065K
代理商： AM79C970A
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AMD
P R E L I M I N A R Y
22
Am79C970A
PIN DESCRIPTION
PCI Interface
AD[31:0]
Address and Data
Address and data are multiplexed on the same bus in-
terface pins. During the first clock of a transaction
AD[31:0] contain a physical address (32 bits). During
the subsequent clocks AD[31:0] contain data. Byte or-
dering is little endian by default. AD[7:0] are defined as
least significant byte and AD[31:24] are defined as the
most significant byte. For FIFO data transfers, the
PCnet-PCI II controller can be programmed for big
endian byte ordering. See CSR3, bit 2 (BSWP) for
more details.
Input/Output
During the address phase of the transaction, when the
PCnet-PCI II controller is a bus master, AD[31:2] will
address the active Double Word (DWord). The
PCnet-PCI II controller always drives AD[1:0] to ‘00’ dur-
ing the address phase indicating linear burst order.
When the PCnet-PCI II controller is not a bus master,
the AD[31:0] lines are continuously monitored to deter-
mine if an address match exists for slave transfers.
During the data phase of the transaction, AD[31:0] are
driven by the PCnet-PCI II controller when performing
bus master write and slave read operations. Data on
AD[31:0] is latched by the PCnet-PCI II controller when
performing bus master read and slave write operations.
When
RST
is active, AD[31:0] are inputs for NAND
tree testing.
C/
BE
[3:0]
Bus Command and Byte Enables
Bus command and byte enables are multiplexed on the
same bus interface pins. During the address phase of
the transaction, C/
BE
[3:0] define the bus command.
During the data phase C/
BE
[3:0] are used as byte en-
ables. The byte enables define which physical byte
lanes carry meaningful data. C/
BE
0 applies to byte 0
(AD[7:0]) and C/
BE
3 applies to byte 3 (AD[31:24]). The
function of the byte enables is independent of the byte
ordering mode (BSWP, CSR3, bit 2).
Input/Output
When
RST
is active, C/
BE
[3:0] are inputs for NAND
tree testing.
CLK
Clock
This clock is used to drive the system bus interface and
the internal buffer management unit. All bus signals are
sampled on the rising edge of CLK and all parameters
Input
are defined with respect to this edge. The PCnet-PCI II
controller operates over a range of 0 MHz to 33 MHz.
This clock is not used to drive the network functions.
When
RST
is active, CLK is an input for NAND
tree testing.
DEVSEL
Device Select
The PCnet-PCI II controller drives
DEVSEL
when it
detects a transaction that selects the device as a target.
The device samples
DEVSEL
to detect if a target
claims a transaction that the PCnet-PCI II controller
has initiated.
Input/Output
When
RST
is active,
DEVSEL
is an input for NAND
tree testing.
FRAME
Cycle Frame
FRAME
is driven by the PCnet-PCI II controller when it
is the bus master to indicate the beginning and duration
of a transaction.
FRAME
is asserted to indicate a bus
transaction is beginning.
FRAME
is asserted while data
transfers continue.
FRAME
is deasserted before the fi-
nal data phase of a transaction. When the PCnet-PCI II
controller is in slave mode, it samples
FRAME
to deter-
mine the address phase of transaction.
Input/Output
When
RST
is active,
FRAME
is an input for NAND
tree testing.
GNT
Bus Grant
This signal indicates that the access to the bus has been
granted to the PCnet-PCI II controller.
Input
The PCnet-PCI II controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts
GNT
without an active
REQ
from the PCnet-PCI II controller,
the device will drive the AD[31:0], C/
BE
[3:0] and
PAR lines.
When
RST
is active,
GNT
is an input for NAND
tree testing.
IDSEL
Initialization Device Select
This signal is used as a chip select for the
PCnet-PCI II controller during configuration read and
write transactions.
Input
When
RST
is active, IDSEL is an input for NAND
tree testing.
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