參數(shù)資料
型號: AM79C970A
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述: PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器,適用于PCI總線產品
文件頁數(shù): 215/219頁
文件大小: 1065K
代理商: AM79C970A
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E-1
Am79C970A
PCnet-PCI II and PCnet-PCI Differences
APPENDIX E
OVERVIEW
This appendix summarizes the enhancements of the
PCnet-PCI II controller over the PCnet-PCI controller.
The feature summary is followed by a detailed list of all
register bit changes. The document also compares the
pinout of the PCnet-PCI II controller with the pinout of
the PCnet-PCI and PCnet-SCSI (also known as Golden
Gate) to show that the Flex-I/O footprint is continued to
be supported.
NEW FEATURES
I
Three Volt support for PCI bus interface
I
Full Duplex Ethernet
I
272-byte Transmit FIFO, 256-byte Receive FIFO
I
Enhanced PCI bus transfer cycles:
No more address stepping
Initialization Block read in non-burst (default) or
burst mode
Added new software style and reordered the
descriptor entries to allow burst transfers for
both, descriptor read and write accesses
FIFO DMA bursts length programmable from 1
to indefinite
Type of memory command for burst read trans-
fers programmable to be either Memory Read
Line or Memory Read Multiple (controlled by
MEMCMD, BCR18, bit 9)
Support for fast back-to-back slave transactions
even when the first transaction is addressing a
different target MEMCMD, BCR18, bit 9)
Enhanced disconnect of I/O burst access
I
Allows I/O resources to be memory mapped
I
Eight-bit programmable PCI Latency Timer.
MIN_GNT and MAX_LAT programmable via
EEPROM
I
System interrupt for data parity error, master abort
or target abort in master cycles
I
Network activity is terminated in an orderly se-
quence after a master or target abort
I
Advanced parity error handling. Mode has enable
bit and status bit in RMD1 and TMD1. All network
activity is terminated in an orderly sequence. Will
only work with 32-bit software structures.
I
All registers in the PCI configuration space are
cleared by H_RESET
I
Expansion ROM interface supporting devices of up
to 64 K x 8. One external address latch is required.
I
Reading from the S_RESET port returns
TRDY
right away
I
REQ
deassertion programmable to adapt to the
requirements of some embedded systems
I
INTA
pin programmable for pulse mode to adapt to
the requirements of some embedded systems
I
Some previously reserved locations in the
EEPROM map are now used for new features
I
Suspend mode for graceful stop and access to
the CSR without reinitialization
I
User Interrupt
I
Reduced number of transmit interrupts:
Transmit OK disable (CSR5, bit 15). When bit
is set to ONE, a transmit interrupt is only gener-
ated on frames that suffer an error.
Last Transmit Interrupt. TMD1, bit 28 is read by
the PCnet-PCI II controller to determine if an
interrupt should be generated at the end of the
frame. Only interrupts for successful transmis-
sion can be suppressed. Enabled by LTINTEN
(CSR5, bit 14).
I
Disable Transmit Stop on Underflow (CSR3, bit 6)
bit. PCnet-PCI controller recovers automatically
from transmit underflow.
I
Interrupt indication when coming out of sleep mode
I
Interrupt indication for Excessive Deferral
I
Address match information in Receive Descriptor
I
Asserting
SLEEP
shuts down the entire device
I
S_RESET (reading the RESET register) does not
affect the TMAU, except for the T-MAU in snooze
mode
I
LED registers programmable via EEPROM.
I
Magic Packet Mode
I
EADI interface. Multiplexed with the same LED
pins as for the PCnet-32.
I
GPSI interface. Multiplexed with the Expansion
ROM interface. Use of the Expansion ROM first,
then configuring the pins to the GPSI mode
is supported.
I
JTAG interface
I
Fourth LED supported
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