E-1
Am79C970A
PCnet-PCI II and PCnet-PCI Differences
APPENDIX E
OVERVIEW
This appendix summarizes the enhancements of the
PCnet-PCI II controller over the PCnet-PCI controller.
The feature summary is followed by a detailed list of all
register bit changes. The document also compares the
pinout of the PCnet-PCI II controller with the pinout of
the PCnet-PCI and PCnet-SCSI (also known as Golden
Gate) to show that the Flex-I/O footprint is continued to
be supported.
NEW FEATURES
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Three Volt support for PCI bus interface
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Full Duplex Ethernet
I
272-byte Transmit FIFO, 256-byte Receive FIFO
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Enhanced PCI bus transfer cycles:
—
No more address stepping
—
Initialization Block read in non-burst (default) or
burst mode
—
Added new software style and reordered the
descriptor entries to allow burst transfers for
both, descriptor read and write accesses
—
FIFO DMA bursts length programmable from 1
to indefinite
—
Type of memory command for burst read trans-
fers programmable to be either Memory Read
Line or Memory Read Multiple (controlled by
MEMCMD, BCR18, bit 9)
—
Support for fast back-to-back slave transactions
even when the first transaction is addressing a
different target MEMCMD, BCR18, bit 9)
—
Enhanced disconnect of I/O burst access
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Allows I/O resources to be memory mapped
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Eight-bit programmable PCI Latency Timer.
MIN_GNT and MAX_LAT programmable via
EEPROM
I
System interrupt for data parity error, master abort
or target abort in master cycles
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Network activity is terminated in an orderly se-
quence after a master or target abort
I
Advanced parity error handling. Mode has enable
bit and status bit in RMD1 and TMD1. All network
activity is terminated in an orderly sequence. Will
only work with 32-bit software structures.
I
All registers in the PCI configuration space are
cleared by H_RESET
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Expansion ROM interface supporting devices of up
to 64 K x 8. One external address latch is required.
I
Reading from the S_RESET port returns
TRDY
right away
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REQ
deassertion programmable to adapt to the
requirements of some embedded systems
I
INTA
pin programmable for pulse mode to adapt to
the requirements of some embedded systems
I
Some previously reserved locations in the
EEPROM map are now used for new features
I
Suspend mode for graceful stop and access to
the CSR without reinitialization
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User Interrupt
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Reduced number of transmit interrupts:
—
Transmit OK disable (CSR5, bit 15). When bit
is set to ONE, a transmit interrupt is only gener-
ated on frames that suffer an error.
—
Last Transmit Interrupt. TMD1, bit 28 is read by
the PCnet-PCI II controller to determine if an
interrupt should be generated at the end of the
frame. Only interrupts for successful transmis-
sion can be suppressed. Enabled by LTINTEN
(CSR5, bit 14).
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Disable Transmit Stop on Underflow (CSR3, bit 6)
bit. PCnet-PCI controller recovers automatically
from transmit underflow.
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Interrupt indication when coming out of sleep mode
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Interrupt indication for Excessive Deferral
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Address match information in Receive Descriptor
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Asserting
SLEEP
shuts down the entire device
I
S_RESET (reading the RESET register) does not
affect the TMAU, except for the T-MAU in snooze
mode
I
LED registers programmable via EEPROM.
I
Magic Packet Mode
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EADI interface. Multiplexed with the same LED
pins as for the PCnet-32.
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GPSI interface. Multiplexed with the Expansion
ROM interface. Use of the Expansion ROM first,
then configuring the pins to the GPSI mode
is supported.
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JTAG interface
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Fourth LED supported