參數(shù)資料
型號(hào): CP2200-GQ
廠(chǎng)商: Silicon Laboratories Inc
文件頁(yè)數(shù): 105/108頁(yè)
文件大?。?/td> 0K
描述: IC ETH CTRLR SNGL-CHIP 48TQFP
標(biāo)準(zhǔn)包裝: 250
控制器類(lèi)型: 以太網(wǎng)控制器,MAC/10Base-T
接口: 并行/串行
電源電壓: 3.1 V ~ 3.6 V
電流 - 電源: 75mA
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 627 (CN2011-ZH PDF)
配用: 336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR
其它名稱(chēng): 336-1312
CP2200/1
96
Rev. 1.0
16. Parallel Interface
The CP2200/1 has an 8-bit parallel host interface used to access the direct registers on the device. The parallel
interface supports multiplexed or non-multiplexed operation using the Intel or Motorola bus format. The MUXEN
pin can be driven high to place the device in multiplexed operation or driven low to select non-multiplexed
operation. The MOTEN pin can be driven high to place the device in Motorola bus format or driven low to place the
device in Intel bus format.
Notes:
1. The CP2201 (28-pin package) can only be used in multiplexed mode.
2. The PCB traces connecting RD, WR, CS, ALE, and all address and data lines should be matched such that the
propagation delay does not vary by more than 5ns between any two signals.
A parallel interface read or write operation typically requires 260 ns (non-multiplexed) or 300 ns (multiplexed) to
transfer one byte of data. If back-to-back operations are scheduled on a non-multiplexed bus, data rates up to
30 Mbps can be achieved. Tables 26 through 29 provide detailed information about bus timing in each mode.
16.1. Non-Multiplexed Intel Format
Figure 22. Nonmuxed Intel READ
Valid Address
T
VD2
T
HOLD
T
VD1
T
AS
A[7:0]
D[7:0]
RD
Valid Data
T
RD
T
AHR
Notes:
1. CS must be asserted with or before RD.
2. WR must remain de-asserted during a READ.
Valid Address
T
DH
T
HOLD
T
WR
T
AS
A[7:0]
D[7:0]
WR
Valid Data
T
AHW
T
DS
Notes:
1. CS must be asserted with or before WR.
2. RD must remain de-asserted during a WRITE.
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