參數(shù)資料
型號(hào): CP2200-GQ
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 89/108頁(yè)
文件大小: 0K
描述: IC ETH CTRLR SNGL-CHIP 48TQFP
標(biāo)準(zhǔn)包裝: 250
控制器類(lèi)型: 以太網(wǎng)控制器,MAC/10Base-T
接口: 并行/串行
電源電壓: 3.1 V ~ 3.6 V
電流 - 電源: 75mA
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 627 (CN2011-ZH PDF)
配用: 336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR
其它名稱(chēng): 336-1312
CP2200/1
Rev. 1.0
81
Indirect Register 1. MACCN: MAC Control Register
Bit 15:
Reserved. Read = varies; Must write 0b.
Bit 14:
RANDRST: Random Number Generator Reset
Writing a ‘1’ to this bit resets the random number generator within the transmit function.
Bits 13–5:Reserved. Read = varies; Must write 000000000b.
Bit 4:
LOOPBCK: Loopback Mode Enable Bit
Note: MAC Loopback Mode is independent of the physical layer loopback mode.
0: Normal operation.
1: MAC transmit data is internally looped back as MAC receive data.
Bit 3:
TXPAUSE: TX Flow Control Enable Bit (Full-Duplex Only)
0: PAUSE control frames are blocked.
1: PAUSE control frames are allowed to pass through the MAC.
Bit 2:
RXPAUSE: RX Flow Control Enable Bit (Full-Duplex Only)
0: PAUSE control frames received from the physical layer are ignored.
1: PAUSE control frames received from the physical layer are acted upon.
Bit 1:
Reserved. Read = 0; Must write 0b.
Bit 0:
RCVEN: Receive Enable
0: The MAC blocks control frames from reaching the receive interface. The MAC blocks all received
packets from the receive interface.
1: The MAC allows received packets to reach the receive interface.
R/W
Reserved RANDRST
Reserved
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
R/W
Default Value
Reserved
LOOPBCK TXPAUSE RXPAUSE Reserved
RCVEN
0x8000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MACADDR:
0x00
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