參數(shù)資料
型號： CP2200-GQ
廠商： Silicon Laboratories Inc
文件頁數(shù)： 2/108頁
文件大?。?/td> 0K
描述： IC ETH CTRLR SNGL-CHIP 48TQFP
標(biāo)準(zhǔn)包裝： 250
控制器類型： 以太網(wǎng)控制器，MAC/10Base-T
接口： 并行/串行
電源電壓： 3.1 V ~ 3.6 V
電流 - 電源： 75mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
產(chǎn)品目錄頁面： 627 (CN2011-ZH PDF)
配用： 336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR
其它名稱： 336-1312
CP2200/1
10
Rev. 1.0
5. Pinout and Package Definitions
Table 4. CP2200/1 Pin Definitions
Name
Pin Numbers
Type
Description
48-pin
28-pin
AV+
5
3
Power In 3.1–3.6 V Analog Power Supply Voltage Input.
AGND
4
2
Analog Ground
VDD1
13
8
Power In 3.1–3.6 V Digital Power Supply Voltage Input.
DGND1
14
9
Digital Ground
VDD2
30
19
Power In 3.1–3.6 V Digital Power Supply Voltage Input.
DGND2
31
20
Digital Ground
RST
15
10
D I/O
Device Reset. Open-drain output of internal POR and VDD monitor.
An external source can initiate a system reset by driving this pin low
for at least 15 s.
LINK
3*
—
D Out
Link LED. Push-pull output driven high when valid 10BASE-T link
pulses are detected (Link Good) and driven low when valid
10BASE-T link pulses are not detected (Link Fail).
ACT
2*
—
D Out
Activity LED. Push-pull output driven high for 50 ms when any
packet is transmitted or received and driven low all other times.
LA
—
1*
D Out
Link or Activity LED. Push-pull output driven high when valid link
pulses are detected (Link Good) and driven low otherwise (Link
Fail). The output is toggled for each packet transmitted or received,
then returns to its original state after 50 ms.
XTAL1
46
28
A In
Crystal Input. This pin is the return for the external oscillator driver.
This pin can be overdriven by an external CMOS clock.
XTAL2
45*
27*
A Out
Crystal Output. This pin is the excitation driver for a quartz crystal.
TX+
9
6
A Out
10BASE-T Transmit, Differential Output (Positive).
TX–
10
7
A Out
10BASE-T Transmit, Differential Output (Negative).
RX+
7
5
A In
10BASE-T Receive, Differential Input (Positive).
RX–
6
4
A In
10BASE-T Receive, Differential Input (Negative).
MOTEN
43
26
D In
Motorola Bus Format Enable. This pin should be tied directly to VDD
for Motorola bus format or directly to GND for Intel bus format.
MUXEN
44
—
D In
Multiplexed Bus Enable. This pin should be tied directly to VDD for
multiplexed bus mode or directly to GND for non-multiplexed bus
mode.
INT
42
25
D Out
Interrupt Service Request. This pin provides notification to the host.
*Note: Pins can be left unconnected when not used.
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