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參數(shù)資料
| 型號： | CP2200-GQ |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 34/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETH CTRLR SNGL-CHIP 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/10Base-T |
| 接口： | 并行/串行 |
| 電源電壓： | 3.1 V ~ 3.6 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 627 (CN2011-ZH PDF) |
| 配用： | 336-1316-ND - KIT EVAL FOR CP2201 ETH CTRLR |
| 其它名稱： | 336-1312 |
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CP2200/1
Rev. 1.0
31
Register 5. INT0: Interrupt Status Register 0 (Self-Clearing)
Note: Reading this register will clear all INT0 interrupt flags.
Bit 7:
EOPINT: End of Packet Interrupt Flag
0: The last byte of a packet has not been read since the last time EOPINT was cleared.
1: The last byte of a packet has been read.
Bit 6:
RXEINT: Receive FIFO Empty Interrupt Flag
0: The receive FIFO has not been empty since the last time RXEINT was cleared.
1: The receive FIFO is empty.
Bit 5:
SELFINT: Self Initialization Complete Interrupt Flag
0: Self Initialization has not completed since the last time SELFINT was cleared.
1: Self Initialization has completed.
Bit 4:
OSCINT: Oscillator Initialization Complete Interrupt Flag
0: Oscillator Initialization has not completed since the last time OSCINT was cleared.
1: Oscillator Initialization has completed.
Bit 3:
FLWEINT: Flash Write/Erase Operation Complete Interrupt Flag
0: A Flash write or erase operation has not completed since the last time FLWEINT was cleared.
1: A Flash write or erase operation has completed.
Bit 2:
TXINT: Packet Transmitted Interrupt Flag
0: A packet transmission has not completed since the last time TXINT was cleared.
1: A packet has been transmitted.
Bit 1:
RXFINT: Receive FIFO Full Interrupt Flag
0: The receive FIFO has not been full since the last time RXFINT was cleared.
1: The receive FIFO is full.
Bit 0:
RXINT: Packet Received Interrupt Flag
0: A packet has not been added to the receive buffer since the last time RXINT was cleared.
1: A packet has been added to the receive buffer.
RC
Reset Value
EOPINT
RXEINT
SELFINT
OSCINT
FLWEINT
TXINT
RXFINT
RXINT
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x63
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