參數(shù)資料
型號: DM9801A
文件頁數(shù): 25/60頁
文件大?。?/td> 605K
代理商: DM9801A
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Final
Version: DM9801A-DS-F01
May 30, 2001
25
Basic Mode Status Register (BMSR) - Register 1
Bit
Bit Name
1.15
100Base-T4
Default
0,RO/P
Description
Reserved:
The DM9801A does not support this function. This bit is
permanently set to 0
Reserved:
The DM9801A does not support this function. This bit is
permanently set to 0
Reserved:
The DM9801A does not support this function. This bit is
permanently set to 0
Reserved:
The DM9801A does not support this function. This bit is
permanently set to 0
Reserved:
The DM9801A supports half Duplex Operation only. This bit is
permanently set to 1
Reserved:
Write as 0, ignore on read
MII Frame Preamble Suppression:
1=PHY will accept management frames with preamble suppressed
0=PHY will not accept management frames with preamble suppressed
Auto-negotiation Complete:
The DM9801A does not support this function. This bit is
permanently set to 1
Remote Fault:
The DM9801A does not support this function. This bit is
permanently set to 0
Auto Configuration Ability:
The DM9801A does not support this function. This bit is
permanently set to 0
Link Status:
1=Valid link established
0=Link not established
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the Link Status bit to be
cleared and remain cleared until it is read via the management
interface
Jabber Detect:
The DM9801A does not support this function. This bit is
permanently set to 0
Extended Capability:
The DM9801A does not support this function. This bit is
permanently set to 0
1.14
100Base-TX
Full Duplex
0,RO/P
1.13
100Base-TX
Half Duplex
0,RO/P
1.12
10Base-T
Full Duplex
0,RO/P
1.11
10Base-T
Half Duplex
1,RO/P
1.10-1.7
Reserved
0,RO
1.6
MF Preamble
Suppression
0,RO/P
1.5
Auto-negotiation
Complete
1,RO/P
1.4
Remote Fault
0,RO/P
1.3
Auto-negotiation
Ability
0,RO/P
1.2
Link Status
0,RO/LL
1.1
Jabber Detect
0,RO/P
1.0
Extended
Capability
0,RO/P
PHY ID Identifier Register #1 (PHYIDR1) - Register 2
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9801A. The Identifier consists of a
concatenation of the
Organizationally Unique Identifier
(OUI), a vendor's model number, and a model revision number.
DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
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