參數(shù)資料
型號: DM9801A
文件頁數(shù): 56/60頁
文件大?。?/td> 605K
代理商: DM9801A
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
56
Final
Version: DM9801A-DS-F01
May 30, 2001
SPI Master Mode Timing Diagram
SCLK
SO
SCS#
SI
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5
Data Byte 0
TDLYscs
l
TDLYsov
TWIDTHclk
h
TWIDTHclk
l
TSETsi
v
Instruction Byte
Address Byte
b7
b6
SPI Master Timing Parameters
Symbol
TWIDTHclkh
TWIDTHclkl
TDLYscsl
TDLYsov
TSETsiv
Parameter
Min.
790
790
Typ.
Max.
810
810
40
60
Unit
ns
ns
ns
ns
ns
Conditions
Positive half-cycle pulse width
Negative half-cycle pulse width
Falling clock edge to SCS# low
Falling clock edge to SO valid
SI valid to rising clock edge
40
20
SPI Slave Mode Timing Diagram
SCLK
SI
SCS#
SO
TSETscsl
TSETsiv
TWIDTHclk
h
TWIDTHclkl
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5
Instruction Byte
Address Byte
b7 b6 b5
b4 b3 b2 b1 b0 b7 b6 b5
(High-Z when writing)
Data Byte
TDLYsov
TDLYsoz
TSETscsh
Data Byte
(Don't care on read)
SPI Master Timing Parameters
Symbol
TWIDTHclkh
TWIDTHclkl
TSETscsl
TSETscsh
TDLYsov
TDLYsoz
TSETsiv
Parameter
Min.
400
400
50
50
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
Conditions
Positive half-cycle pulse width
Negative half-cycle pulse width
SCS# low to rising clock edge
SCS# high to rising edge clock
Falling edge clock to SO valid
Falling edge clock to SO tri-state
SI valid to rising clock edge
50
100
50
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