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參數(shù)資料
| 型號： | DM9801A |
| 文件頁數(shù)： | 6/60頁 |
| 文件大?。?/td> | 605K |
| 代理商： | DM9801A |
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DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
6
Final
Version: DM9801A-DS-F01
May 30, 2001
Pin Description
(Continued)
PHY Address Interface:
PHYAD[4:0] provides up to 32 unique PHY address. An address selection of all zeros (00000) will result in a
PHY isolation condition. See the isolate bit description in the BMCR, address 00.
68
PHYADSEL
(PHYAD0)
Or
SCLK
both CONFIG1 and CONFIG0 are not set to 1.
0 = 0x01 address
1 = 0x1F address
PHY Address 0 (MII Mode, i.e. INTFSEL = 0 or GM_MODE, i.e.
INTFSEL=1, CONFIG1=1, and CONFIG0=1):
PHY address bit 0 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1.
Serial Interface Clock (Standard GPSI Mode, INTFSEL = 1):
SCLK is a bi-directional clock signal used to synchronize SI, SO and SCS#
to and from the DM9801A SPI bus.
8
PHYAD1
I/O,
Z
CONFIG1=1, and CONFIG0=1):
PHY address bit 1 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
9
PHYAD2
I/O,
Z
CONFIG1=1, and CONFIG0=1):
PHY address bit 2 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
10
PHYAD3
I/O,
Z
INTFSEL=1, CONFIG1=1, and CONFIG0=1:
PHY address bit 3 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
47
PHYAD4
I/O,
Z
INTFSEL=1, CONFIG1=1, and CONFIG0=1:
PHY address bit 4 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
I/O,Z
MII Serial Management PHY Address Select (MII Mode, INTFSEL = 0):
PHYADSEL is an input signal that selects one of two PHY addresses within
the 32 address range for the DM9801A MII management interface when
PHY Address 1 (MII Mode, INTFSEL = 0, or GM_MODE, i.e. INTFSEL=1,
PHY Address 2 (MII Mode, INTFSEL = 0, or GM_MODE, i.e. INTFSEL=1,
PHY Address 3 (MII Mode, INTFSEL = 0), or GM_MODE, i.e.
PHY Address 4 (MII Mode, INTFSEL = 0), or GM_MODE, i.e.
Pin Description
(Continued)
Pin No.
Configuration and Control Interface:
64
RESET#
Pin Name
I/O
Description
I
Reset:
Active Low input that initializes the DM9801A. Should remain low for 10ms
after VCC has stabilized at 3.3Vdc (nominal) before it transitions to high.
Configuration Select 1:0:
These input pins select the DM9801A configuration from a reset condition.
63
62
CONFIG0
CONFIG1
I
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