參數(shù)資料
型號(hào)： DM9801A
文件頁(yè)數(shù)： 41/60頁(yè)
文件大?。?/td> 605K
代理商： DM9801A
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Final
Version: DM9801A-DS-F01
May 30, 2001
41
Aid Interval Register - Register 26 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
26.7 -
26.0
Default
0x14, RW
Description
AID_INTERVAL
AID Interval:
This value defines the number of TCLKs (116.7ns) separating AID
symbols.
Aid Inter-Symbol Blanking Interval Register - Register 27 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
Default
27.7 -
27.0
Description
AID_ISBI
0x40, RW
AID Inter Symbol Blanking Interval:
This value defines the number of TCLKs (116.7ns) between AID
pulses for symbol 0.
ISBI Slow Register - Register 28 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
28.7 -
28.0
Default
0x2C, RW
Description
ISBI_SLOW
Inter Symbol Blanking Interval (Low Speed):
This value defines the number of TCLKs (116.7ns) between DATA
pulses for symbol 0 in low speed
ISBI Fast Register - Register 29 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
29.7 -
29.0
Default
0x1C, RW
Description
ISBI_FAST
Inter Symbol Blanking Interval (High Speed):
This value defines the number of TCLKs (116.7ns) between DATA
pulses for symbol 0 in High speed
TX Pulse Width Register - Register 30 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
30.7 -
30.0
Default
0x04, RW
Description
TX_PLS_WIDTH
Transmit Pulse Width:
This value determines the duration in OSC cycles (16.7 ns) that a
transmit pulse lasts.
TX Pulse Cycles Register - Register 31 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
31.7 -
31.0
Default
0x44, RW
Description
TX_PLS_CYCLS
Transmit Pulse Cycles:
The low nibble of this register indicates the number of pulses on the
HNN pins while the high nibble indicates the number of pulses on the
HNP pins.
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