參數(shù)資料
型號: DM9801A
文件頁數(shù): 51/60頁
文件大小: 605K
代理商: DM9801A
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Final
Version: DM9801A-DS-F01
May 30, 2001
51
AC Electrical Characteristics & Timing Waveforms
(Over full range of operating condition unless specified
otherwise)
Analog Transmitter Timing Diagram
HN+/-
tPW
tPWL
tPWH
Symbol
Transmitter (Analog)
t
PW
t
PWH
t
PWL
t
PWH
t
PWL
MII (Media-Independent Interface) Clock Timing
Idle (excluding IFG time)
t
PWH
TX_CLK/RX_CLK Pulse Width
High
t
PWL
TX_CLK/RX_CLK Pulse Width
Low
Preamble (first 64 bits of TX MAC frame)
t
TPWH
TX_CLK Pulse Width High
t
TPWL
TX_CLK Pulse Width Low
t
RPWH
RX_CLK Pulse Width High
t
RPWL
RX_CLK Pulse Width Low
Data (throughout the data phase)
t
PWH
TX_CLK/RX_CLK Pulse Width
High
t
PWL
TX_CLK/RX_CLK Pulse Width
Low
IFG (88 bit times following CRS falling edge)
t
PWH
TX_CLK/RX_CLK Pulse Width
High
t
PWL
TX_CLK/RX_CLK Pulse Width
Low
Notes: 1) During AID interval, RX_CLK and TX_CLK stop for up to 140 us.
2) During Preamble state, RX_CLK stays at Low.
Parameter
Min.
Typ.
Max.
Unit
Conditions
Pulse Width
Pulse Width High
Pulse Width Low
OSC Pulse Width High
OSC Pulse Width Low
133
67
67
25
25
ns
ns
ns
ns
ns
1168
ns
1165
ns
468
466
-
-
ns
ns
ns
ns
468
ns
466
ns
3us
5.6us
3us
23us
468
ns
466
ns
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