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參數(shù)資料
| 型號： | DM9801A |
| 文件頁數(shù)： | 33/60頁 |
| 文件大小： | 605K |
| 代理商： | DM9801A |
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DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
27.1
DIS_LNK
0, RW
Disable Link:
This bit disables link integrity feature.
27.0
FWENA
0, RW
Four Wire Enable:
When read this bit will indicate the status of FWENA (pin 57) as read
during power up. If the FWENA pin status is 1 on power up, this bit can
be written to change the FWENA status. If the FWENA pin status is 0
on power up, writes to this bit are ignored.
Final
Version: DM9801A-DS-F01
May 30, 2001
33
Aid Address Register - Register 28
Bit
Bit Name
28.15 -
28.8
28.7 -
28.0
Default
0x00, RW
Description
Reserved
Reserved:
These bits will always be read as 0.
AID Address:
Unless bit 7 of the Control register is set, the DM9801A is assured to
select a unique AID Address.
Addresses above 0xEF are reserved. Address 0xFF is defined to
indicate a Remote Command.
AID_ADDRESS
0x00, RW
Aid Control Register - Register 29
Bit
Bit Name
29.15 -
29.8
Default
0x40, RW
Description
AID_ISBI
AID Inter Symbol Blanking Interval:
This value defines the number of TCLKs (116.7ns) between AID
pulses for symbol 0.
AID Interval:
This value defines the number of TCLKs (116.7ns) separating AID
symbols.
29.7 -
29.0
AID_INTERVAL
0x14, RW
Symbol Control Register - Register 30
Bit
Bit Name
30.15 -
30.8
Default
0x1C, RW
Description
ISBI_FAST
Inter Symbol Blanking Interval (High Speed):
This value defines the number of TCLKs (116.7ns) between data
pulses for symbol 0 in High speed
Inter Symbol Blanking Interval (Low Speed):
This value defines the number of TCLKs (116.7ns) between data
pulses for symbol 0 in low speed
30.7 -
30.0
ISBI_SLOW
0x2C, RW
TX Signal Control Register - Register 31
Bit
Bit Name
31.15 -
31.8
Default
0x44, RW
Description
TX_PLS_CYCLS
Transmit Pulse Cycles:
The low nibble of this register indicates the number of pulses on the
HNN pins while the high nibble indicates the number of pulses on the
HNP pins.
Transmit Pulse Width:
This value determines the duration in OSC cycles (16.7 ns) that a
transmit pulse lasts.
31.7 -
31.0
TX_PLS_WIDTH
0x04, RW
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相關代理商/技術參數(shù) |
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