參數(shù)資料
型號(hào)： DM9801A
文件頁數(shù)： 30/60頁
文件大小： 605K
代理商： DM9801A
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
17.6
RX_PWR
0, RO
Receive Power:
This bit is an indication of the current receive signal power.
1= The receive signal power is high.
0= The receive signal power is low.
17.5
RX_SPD
0, RO
Receive Speed:
This bit is an indication of the current receive speed.
1= The receive speed is high.
0= The receive speed is low.
17.4
RX_VER
0, RO
Receive Version:
This bit is an indication of the current receive version.
1= The receive version is not version 0.
0= The receive version is version 0.
17.3 -
17.0
Write as 0, ignore on read
30
Final
Version: DM9801A-DS-F01
May 30, 2001
Reserved
<0101>, RW
Reserved:
IMASK (Interrupt Mask) Register - Register 18
Bit
Bit Name
18.15 –
18.10
Interrupts
Default
0,RW
Description
Software
Software Interrupts:
1= Software interrupts will not activate the INT# pin
0= Software interrupts will activate the INT# pin
Mask RXPCOM Valid:
1= RX_PCOM_VAL will not activate the INT# pin
0= RX_PCOM_VAL will activate the INT# pin
Mask TXPCOM Ready:
1= TX_PCOM_RDY will not activate the INT# pin
0= TX_PCOM_RDY will activate the INT# pin
Reserved:
Write as 0, ignore on read
Mask Packet Received:
1= Packet Received will not activate the INT# pin
0= Packet Received will activate the INT# pin
Packet Transmitted:
1= Packet Transmitted will not activate the INT# pin
0= Packet Transmitted will activate the INT# pin
Remote Command Received:
1= Remote Command Received will not activate the INT# pin
0= Remote Command Received will activate the INT# pin
Remote Command Sent:
1= Remote Command Sent will not activate the INT# pin
0= Remote Command Sent will activate the INT# pin.
18.9
MSK_RX_PCOM
0,RW
18.8
MSK_TX_PCOM
0,RW
18.7 –
18.4
18.3
Reserved
0,RW
MSK_PKT_RCV
0,RW
18.2
MSK_PKT_XMIT
0,RW
18.1
MSK_RMT_RCV
0,RW
18.0
MSK_CMD_SNT
0,RW
ISTAT (Interrupt Status) Register - Register 19
This register reports the state of each interrupt source regardless of the state of the IMASK Register.
Bit
Bit Name
Default
19.15 –
19.10
Interrupts
Description
Software
0,RW
Software Interrupts:
When set any bit of those registers indicates software interrupt
is on.
RXPCOM Valid:
When set this bit indicates a non-null RX_PCOM has been
received.
Accessing the high byte of the RX_PCOM register clears this
bit.
19.9
RX_PCOM_VAL
0,RW
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