參數(shù)資料
型號(hào): DM9801A
文件頁數(shù): 29/60頁
文件大?。?/td> 605K
代理商: DM9801A
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
16.9
CMD_LO_SPD
0,RW
Command Low Speed:
1= Transmit speed is set to low
0= Normal operation
Remote commands will be issued if this bit is set
16.8
CMD_HI_SPD
0,RW
Command High Speed:
1= Transmit speed is set to high
0= Normal operation
Remote commands will be issued if this bit is set
16.7
AID_ADR_NEG
0,RW
AID Address Negotiation:
1= Stop AID address negotiation
0= Normal operation
16.6
CLR_NS_EVNT
0,RW
Clear Noise Event Register:
1= Clear the Noise Event Register
0= Normal operation
16.5
SLC_LVL_ADP
0,RW
Slice Level Adaptation:
1= Slice level adaptation is disabled (stopped).
0= Slice level adaptation is enabled
16.4
PWR_DWN
0,RW
Power Down:
Writing a 1 to this bit will cause DM9801A to enter Sleep mode
and power down all circuits except the oscillator and clock
generator circuit. To exit Sleep mode, write 0 to this bit position.
The prior configuration will be retained when the sleep state is
terminated, but the state machine will be reset
16.3
Reserved
0,RW
Reserved:
This bit must be written as 0
16.2
Speed
1, RW
Speed:
1= high speed
0= low speed
This bit indicates the network speed is set to high as selected
by the status of the SPDSEL pin during power-up/reset.
16.1
Power
0, RW
Power:
1= high power
0= low power
This bit indicates the network power is set to high as selected
by the status of the PWRSEL pin during power-up/reset.
16.0
Reserved
1,RW
Reserved:
This bit must be written as 1
Final
Version: DM9801A-DS-F01
May 30, 2001
29
Status Register - Register 17
Bit
17.15 –
17.11
17.10
Bit Name
Reserved
Default
0, RW
Description
Reserved:
Write as 0, ignore on read
Link Status:
This bit reports the Link Status of the DM9801A
Disable LED Stretchers:
This bit disables LED pulse stretchers
Reserved:
Write as 0, ignore on read
Receiving station reserved.
LINK_STA
0, RO
17.9
DIS_LED_STR
0, RW
17.8
Reserved
0, RW
17.7
RX_RESERVED
0, RW
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