參數(shù)資料
型號(hào): DS21FT42
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 101/145頁
文件大?。?/td> 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/101
TAP Controller State Machine
Figure 23-2
23.3
Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output and is 3
bits in length. When the TAP controller enters the Shift-IR state, the instruction shift
register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising
edge on JTCLK with JTMS low will shift the data one stage towards the serial output at
JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS
high will move the controller to the Update-IR state The falling edge of that same JTCLK
will latch the data in the instruction shift register to the instruction parallel output.
Instructions supported by the DS21Q42 with their respective operational binary codes are
shown in Table 23-1.
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
Select
DR-Scan
Capture DR
Shift DR
Exit DR
Pause DR
Exit2 DR
Update DR
Select
IR-Scan
Capture IR
Shift IR
Exit IR
Pause IR
Exit2 IR
Update IR
Test Logic
Reset
Run Test/
Idle
0
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