參數(shù)資料
型號: DS21FT42
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 79/145頁
文件大?。?/td> 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1239
2. Set SBOC bit in TBOC=1
19.1.3
HDLC/BOC Register Description
HCR: HDLC CONTROL REGISTER
(Address = 00 Hex)
(MSB)
RBR
(LSB)
TCRCD
RHR
TFS
THR
TABT
TEOM
TZSD
SYMBOL
POSITION
NAME AND DESCRIPTION
RBR
HCR.7
Receive BOC Reset.
A 0 to 1 transition will reset the BOC circuitry.
Must be cleared and set again for a subsequent reset.
Receive HDLC Reset.
A 0 to 1 transition will reset the HDLC
controller. Must be cleared and set again for a subsequent reset.
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
Transmit HDLC/BOC Reset.
A 0 to 1 transition will reset both the
HDLC controller and the transmit BOC circuitry. Must be cleared and
set again for a subsequent reset.
Transmit Abort.
A 0 to 1 transition will cause the FIFO contents to be
dumped and one FEh abort to be sent followed by 7Eh or FFh
flags/idle until a new packet is initiated by writing new data into the
FIFO. Must be cleared and set again for a subsequent abort to be sent.
Transmit End of Message.
Should be set to a one just before the last
data byte of a HDLC packet is written into the transmit FIFO at THFR.
The HDLC controller will clear this bit when the last byte has been
transmitted.
Transmit Zero Stuffer Defeat.
Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
RHR
HCR.6
TFS
HCR.5
THR
HCR.4
TABT
HCR.3
TEOM
HCR.2
TZSD
HCR.1
TCRCD
HCR.0
HSR: HDLC STATUS REGISTER
(Address = 01 Hex)
(MSB)
RBOC
(LSB)
TMEND
RPE
RPS
RHALF
RNE
THALF
TNF
SYMBOL
POSITION
NAME AND DESCRIPTION
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