參數(shù)資料
型號(hào)： DS21FT42
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 38/145頁
文件大?。?/td> 466K
代理商： DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1238
CCR1: COMMON CONTROL REGISTER 1
(Address=37 Hex)
(MSB)
TESE
(LSB)
FLB
ODF
RSAO
TSCLKM
RSCLKM
RESE
PLB
SYMBOL
POSITION
NAME AND DESCRIPTION
TESE
CCR1.7
Transmit Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
Output Data Format.
0 = bipolar data at TPOS and TNEG
1 = NRZ data at TPOS; TNEG = 0
Receive Signaling All One’s.
This bit should not be enabled if
hardware signaling is being utilized. See Section 14 for more details.
0 = allow robbed signaling bits to appear at RSER
1 = force all robbed signaling bits at RSER to one
TSYSCLK Mode Select.
0 = if TSYSCLK is 1.544 MHz
1 = if TSYSCLK is 2.048 MHz
RSYSCLK Mode Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz
Receive Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
Payload Loopback.
0 = loopback disabled
1 = loopback enabled
Framer Loopback.
0 = loopback disabled
1 = loopback enabled
ODF
CCR1.6
RSAO
CCR1.5
TSCLKM
CCR1.4
RSCLKM
CCR1.3
RESE
CCR1.2
PLB
CCR1.1
FLB
CCR1.0
Payload Loopback
When CCR1.1 is set to a one, the DS21Q42 will be forced into Payload LoopBack (PLB). Normally, this
loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing
applications. In a PLB situation, the DS21Q42 will loop the 192 bits of payload data (with BPVs corrected) from
the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are
not looped back, they are reinserted by the DS21Q42. When PLB is enabled, the following will occur:
1. data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK
2. all of the receive side signals will continue to operate normally
3. the TCHCLK and TCHBLK signals are forced low
4. data at the TSER, and TSIG pins is ignored
5. the TLCLK signal will become synchronous with RCLK instead of TCLK.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21FT42N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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