- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376965 > DS21FT42 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF資料下載
參數(shù)資料
| 型號： | DS21FT42 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 45/145頁 |
| 文件大小： | 466K |
| 代理商： | DS21FT42 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當(dāng)前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1235
11. STATUS AND INFORMATION REGISTERS
There is a set of nine registers per channel that contain information on the current real time
status of a framer in the DS21Q42, Status Register 1 (SR1), Status Register 2 (SR2),
Receive Information Registers 1 to 3 (RIR1/RIR2/RIR3) and a set of four registers for the
onboard HDLC and BOC controller. The specific details on the four registers pertaining to
the HDLC and BOC controller are covered in Section 19 but they operate the same as the
other status registers in the DS21Q42 and this operation is described below.
When a particular event has occurred (or is occurring), the appropriate bit in one of these
nine registers will be set to a one. All of the bits in SR1, SR2, RIR1, RIR2, and RIR3
registers operate in a latched fashion. This means that if an event or an alarm occurs and a
bit is set to a one in any of the registers, it will remain set until the user reads that bit. The
bit will be cleared when it is read and it will not be set again until the event has occurred
again (or in the case of the RBL, RYEL, LRCL, and RLOS alarms, the bit will remain set
if the alarm is still present). There are bits in the four HDLC and BOC status registers that
are not latched and these bits are listed in Section 19.
The user will always precede a read of any of the nine registers with a write. The byte
written to the register will inform the DS21Q42 which bits the user wishes to read and have
cleared. The user will write a byte to one of these registers, with a one in the bit positions
he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the
latest information on. When a one is written to a bit location, the read register will be
updated with the latest information. When a zero is written to a bit position, the read
register will not be updated and the previous value will be held. A write to the status and
information registers will be immediately followed by a read of the same register. The read
result should be logically AND’ed with the mask byte that was just written and this value
should be written back into the same register to insure that bit does indeed clear. This
second write step is necessary because the alarms and events in the status registers occur
asynchronously in respect to their access via the parallel port. This write–read– write scheme
allows an external microcontroller or microprocessor to individually poll certain bits
without disturbing the other bits in the register. This operation is key in controlling the
DS21Q42 with higher–order software languages.
The SR1, SR2, and FDLS registers have the unique ability to initiate a hardware interrupt
via the INT* output pin. Each of the alarms and events in the SR1, SR2, and HSR can be
either masked or unmasked from the interrupt pin via the Interrupt Mask Register 1 (IMR1),
Interrupt Mask Register 2 (IMR2), and HDLC Interrupt Mask Register (HIMR) respectively.
The FIMR register is covered in Section 19. The INTERRUPT STATUS REGISTER can
be used to determine which framer is requesting interrupt servicing and the type of the
request: status or the HDLC controller.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q50N | Telecommunication IC |
| DS21Q55DK | Quad T1/E1/J1 Transceiver Design Kit Daughter Card |
| DS21Q55 | Quad T1/E1/J1 Transceiver |
| DS21Q55N | Quad T1/E1/J1 Transceiver |
| DS21S07A | SCSI Terminator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21FT42N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。