參數(shù)資料
型號: DS21FT42
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 81/145頁
文件大?。?/td> 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1231
RHALF
HIMR.4
Receive FIFO Half Full.
0 = interrupt masked
1 = interrupt enabled
Receive FIFO Not Empty.
0 = interrupt masked
1 = interrupt enabled
Transmit FIFO Half Empty.
0 = interrupt masked
1 = interrupt enabled
Transmit FIFO Not Full.
0 = interrupt masked
1 = interrupt enabled
Transmit Message End.
0 = interrupt masked
1 = interrupt enabled
RNE
HIMR.3
THALF
HIMR.2
TNF
HIMR.1
TMEND
HIMR.0
RHIR: RECEIVE HDLC INFORMATION REGISTER
(Address = 03 Hex)
(MSB)
RABT
(LSB)
OBYTE
RCRCE
ROVR
RVM
REMPTY
POK
CBYTE
SYMBOL
RABT
POSITION
RHIR.7
NAME AND DESCRIPTION
Abort Sequence Detected.
Set whenever the HDLC controller sees 7
or more ones in a row.
CRC Error.
Set when the CRC checksum is in error.
Overrun.
Set when the HDLC controller has attempted to write a byte
into an already full receive FIFO.
Valid Message.
Set when the HDLC controller has detected and
checked a complete HDLC packet.
Empty.
A real–time bit that is set high when the receive FIFO is
empty.
Packet OK.
Set when the byte available for reading in the receive
FIFO at RHFR is the last byte of a valid message (and hence no abort
was seen, no overrun occurred, and the CRC was correct).
Closing Byte.
Set when the byte available for reading in the receive
FIFO at RHFR is the last byte of a message (whether the message was
valid or not).
Opening Byte.
Set when the byte available for reading in the receive
FIFO at RHFR is the first byte of a message.
RCRCE
ROVR
RHIR.6
RHIR.5
RVM
RHIR.4
REMPTY
RHIR.3
POK
RHIR.2
CBYTE
RHIR.1
OBYTE
RHIR.0
NOTE
:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
RBOC: RECEIVE BIT ORIENTED CODE REGISTER
(Address = 04 Hex)
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