參數資料
型號: DS21FT42
元件分類: 通信及網絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數: 89/145頁
文件大?。?/td> 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1239
20. PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION
Each framer in the DS21Q42 has the ability to generate and detect a repeating bit pattern that
is from one to eight bits in length. To transmit a pattern, the user will load the pattern to be
sent into the Transmit Code Definition (TCD) register and select the proper length of the
pattern by setting the TC0 and TC1 bits in the In–Band Code Control (IBCC) register.
Once this is accomplished, the pattern will be transmitted as long as the TLOOP control bit
(CCR3.1) is enabled. Normally (unless the transmit formatter is programmed to not insert
the F–bit position) the framer will overwrite the repeating pattern once every 193 bits to
allow the F–bit position to be sent. See Figure 24-15 for more details. As an example, if the
user wished to transmit the standard “l(fā)oop up” code for Channel Service Units which is a
repeating pattern of ...10000100001... then 80h would be loaded into TDR and the length
would set to 5 bits.
Each framer can detect two separate repeating patterns to allow for both a “l(fā)oop up” code and
a “l(fā)oop down” code to be detected. The user will program the codes to be detected in the
Receive Up Code Definition (RUPCD) register and the Receive Down Code Definition
(RDNCD) register and the length of each pattern will be selected via the IBCC register. The
framer will detect repeating pattern codes in both framed and unframed circumstances with
bit error rates as high as 10**–2. The code detector has a nominal integration period of 48
ms. Hence, after about 48 ms of receiving either code, the proper status bit (LUP at SR1.7
and LDN at SR1.6) will be set to a one. Normally codes are sent for a period of 5 seconds.
it is recommend that the software poll the framer every 100 ms to 1000 ms until 5 seconds
has elapsed to insure that the code is continuously present.
IBCC: IN–BAND CODE CONTROL REGISTER
(Address=12 Hex)
(MSB)
TC1
(LSB)
RDN0
TC0
RUP2
RUP1
RUP0
RDN2
RDN1
SYMBOL
TC1
TC0
RUP2
RUP1
RUP0
RDN2
RDN1
RDN0
POSITION
IBCC.7
IBCC.6
IBCC.5
IBCC.4
IBCC.3
IBCC.2
IBCC.1
IBCC.0
NAME AND DESCRIPTION
Transmit Code Length Definition Bit 1.
See Table 20–1
Transmit Code Length Definition Bit 0.
See Table 20–1
Receive Up Code Length Definition Bit 2.
See Table 20–2
Receive Up Code Length Definition Bit 1.
See Table 20–2
Receive Up Code Length Definition Bit 0.
See Table 20–2
Receive Down Code Length Definition Bit 2.
See Table 20–2
Receive Down Code Length Definition Bit 1.
See Table 20–2
Receive Down Code Length Definition Bit 0.
See Table 20–2
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