參數(shù)資料
型號： DS21FT42
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 75/145頁
文件大?。?/td> 466K
代理商： DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1235
5. Repeat step 4
6. Wait for interrupt, skip to step 4
7. If POK=0, then discard whole packet, if POK=1, accept the packet
8. Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
Transmit a HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current
sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the
THIR register
2. Enable either the THALF or TNF interrupt
3. Read THIR to obtain TFULL status
a. If TFULL=0, then write a byte into the FIFO and skip to next step (special case
occurs when the last byte is to be written, in this case set TEOM=1 before writing
the byte and then skip to step 6)
b. If TFULL=1, then skip to step 5
4. Repeat step 3
5. Wait for interrupt, skip to step 3
6. Disable THALF or TNF interrupt and enable TMEND interrupt
7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted
correctly.
19. FDL/Fs EXTRACTION AND INSERTION
Each Framer/Formatter has the ability to extract/insert data from/ into the Facility Data Link
(FDL) in the ESF framing mode and from/into Fs–bit position in the D4 framing mode.
Since SLC–96 utilizes the Fs–bit position, this capability can also be used in SLC–96
applications. The DS21Q42 contains a complete HDLC and BOC controller for the FDL
and this operation is covered in Section 19.1. To allow for backward compatibility between
the DS21Q42 and earlier devices, the DS21Q42 maintains some legacy functionality for the
FDL and this is covered in Section 19.2. Section 19.3 covers D4 and SLC–96 operation.
Please contact the factory for a copy of C language source code for implementing the FDL on
the DS21Q42.
19.1
HDLC AND BOC CONTROLLER FOR THE FDL
19.1.1
General Overview
The DS21Q42 contains a complete HDLC controller with 64–byte buffers in both the
transmit and receive directions as well as separate dedicated hardware for Bit Oriented Codes
(BOC). The HDLC controller performs all the necessary overhead for generating and
receiving Performance Report Messages (PRM) as described in ANSI T1.403 and the
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參數(shù)描述
DS21FT42N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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