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參數(shù)資料
| 型號： | DS21FT42 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 77/145頁 |
| 文件大?。?/td> | 466K |
| 代理商： | DS21FT42 |
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DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1237
registers are latched and some are real time bits that are not latched. Section 19.1.4 contains
register descriptions that list which bits are latched and which are not. With the latched bits,
when an event occurs and a bit is set to a one, it will remain set until the user reads that bit.
The bit will be cleared when it is read and it will not be set again until the event has
occurred again. The real time bits report the current instantaneous conditions that are
occurring and the history of these bits is not latched.
Like the other status registers in the DS21Q42, the user will always proceed a read of any of
the four registers with a write. The byte written to the register will inform the DS21Q42
which of the latched bits the user wishes to read and have cleared (the real time bits are not
affected by writing to the status register). The user will write a byte to one of these registers,
with a one in the bit positions he or she wishes to read and a zero in the bit positions he or
she does not wish to obtain the latest information on. When a one is written to a bit
location, the read register will be updated with current value and it will be cleared. When a
zero is written to a bit position, the read register will not be updated and the previous value
will be held. A write to the status and information registers will be immediately followed by
a read of the same register. The read result should be logically AND’ed with the mask byte
that was just written and this value should be written back into the same register to insure
that bit does indeed clear. This second write step is necessary because the alarms and events
in the status registers occur asynchronously in respect to their access via the parallel port.
This write–read–write (for polled driven access) or write–read (for interrupt driven access)
scheme allows an external microcontroller or microprocessor to individually poll certain bits
without disturbing the other bits in the register. This operation is key in controlling the
DS21Q42 with higher–order software languages.
Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a
hardware interrupt via the INT* output pin. Each of the events in the HSR can be either
masked or unmasked from the interrupt pin via the HDLC Interrupt Mask Register (HIMR).
Interrupts will force the INT* pin low when the event occurs. The INT* pin will be allowed
to return high (if no other interrupts are present) when the user reads the event bit that caused
the interrupt to occur.
Basic Operation Details
To allow the framer to properly source/receive data from/to the HDLC and BOC controller
the legacy FDL circuitry (which is described in Section 19.2) should be disabled and the
following bits should be programmed as shown:
TCR1.2 = 1 (source FDL data from the HDLC and BOC controller)
TBOC.6 = 1 (enable HDLC and BOC controller)
CCR2.5 = 0 (disable SLC–96 and D4 Fs–bit insertion)
CCR2.4 = 0 (disable legacy FDL zero stuffer)
CCR2.1 = 0 (disable SLC–96 reception)
CCR2.0 = 0 (disable legacy FDL zero stuffer)
IMR2.4 = 0 (disable legacy receive FDL buffer full interrupt)
IMR2.3 = 0 (disable legacy transmit FDL buffer empty interrupt)
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| DS21FT42N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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