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參數(shù)資料
| 型號： | DS21FT42 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 64/145頁 |
| 文件大小： | 466K |
| 代理商： | DS21FT42 |
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DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1234
TCR1.4. In the ESF framing mode, there can be up to four signaling bits per channel (A, B,
C, and D). On multiframe boundaries, the framer will load the values present in the
Transmit Signaling Register into an outgoing signaling shift register that is internal to the
device. The user can utilize the Transmit Multiframe Interrupt in Status Register 2 (SR2.6)
to know when to update the signaling bits. In the ESF framing mode, the interrupt will
come every 3 ms and the user has a full 3ms to update the TSRs. In the D4 framing mode,
there are only two signaling bits per channel (A and B). However in the D4 framing mode,
the framer uses the C and D bit positions as the A and B bit positions for the next
multiframe. The framer will load the values in the TSRs into the outgoing shift register
every other D4 multiframe.
14.2 HARDWARE BASED SIGNALING
Receive Side
In the receive side of the hardware based signaling, there are two operating modes for the
signaling buffer; signaling extraction and signaling re–insertion. Signaling extraction
involves pulling the signaling bits from the receive data stream and buffering them over a
four multiframe buffer and outputting them in a serial PCM fashion on a channel–by–channel
basis at the RSIG output. This mode is always enabled. In this mode, the receive elastic
store may be enabled or disabled. If the receive elastic store is enabled, then the backplane
clock (RSYSCLK) can be either 1.544 MHz or 2.048 MHz. In the ESF framing mode, the
ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG
data is updated once a multiframe (3 ms) unless a freeze is in effect. In the D4 framing mode,
the AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence,
bits 5 and 6 contain the same data as bits 7 and 8 respectively in each channel. The RSIG
data is updated once a multiframe (1.5 ms) unless a freeze is in effect. See the timing
diagrams in Section 24 for some examples.
The other hardware based signaling operating mode called signaling re–insertion can be
invoked by setting the RSRE control bit high (CCR4.7=1). In this mode, the user will
provide a multiframe sync at the RSYNC pin and the signaling data will be re–aligned at
the RSER output according to this applied multiframe boundary. In this mode, the elastic
store must be enabled however the backplane clock can be either 1.544 MHz or 2.048 MHz.
If the signaling re–insertion mode is enabled, the user can control which channels have
signaling re–insertion performed on a channel–by–channel basis by setting the RPCSI
control bit high (CCR4.6) and then programming the RCHBLK output pin to go high in
the channels in which the signaling re–insertion should not occur. If the RPCSI bit is set
low, then signaling re–insertion will occur in all channels when the signaling re–insertion
mode is enabled (RSRE=1). How to control the operation of the RCHBLK output pin is
covered in Section 16.
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| DS21FT44+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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| DS21FT44N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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