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參數(shù)資料
| 型號(hào)： | DS21FT42 |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 72/145頁(yè) |
| 文件大小： | 466K |
| 代理商： | DS21FT42 |
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DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1232
17. ELASTIC STORES OPERATION
Each framer in the DS21Q42 contains dual two–frame (386 bits) elastic stores, one for the
receive direction, and one for the transmit direction. These elastic stores have two main
purposes. First, they can be used to rate convert the T1 data stream to 2.048 Mbps (or a
multiple of 2.048 Mbps) which is the E1 rate. Secondly, they can be used to absorb the
differences in frequency and phase between the T1 data stream and an asynchronous (i.e., not
frequency locked) backplane clock (which can be 1.544 MHz or 2.048 MHz). The backplane
clock can burst at rates up to 8.192 MHz. Both elastic stores contain full controlled slip
capability which is necessary for this second purpose. Both elastic stores within the framer
are fully independent and no restrictions apply to the sourcing of the various clocks that are
applied to them. The transmit side elastic store can be enabled whether the receive elastic
store is enabled or disabled and vice versa. Also, each elastic store can interface to either a
1.544 MHz or 2.048 MHz backplane without regard to the backplane rate the other elastic
store is interfacing.
Two mechanisms are available to the user for resetting the elastic stores. The Elastic Store
Reset (TX - CCR7.4 & RX - CCR7.5) function forces the elastic stores to a depth of one
frame unconditionally. Data is lost during the reset. The second method, the Elastic Store
Align (TX - CCR6.5 & RX - CCR6.6) forces the elastic store depth to a minimum depth of
half a frame only if the current pointer separation is already less then half a frame. If a
realignment occurs data is lost. In both mechanisms, independent resets are provided for
both the receive and transmit elastic stores.
17.1
RECEIVE SIDE
If the receive side elastic store is enabled (CCR1.2=1), then the user must provide either a
1.544 MHz (CCR1.3=0) or 2.048 MHz (CCR1.3=1) clock at the RSYSCLK pin. The user
has the option of either providing a frame/multiframe sync at the RSYNC pin (RCR2.3=1)
or having the RSYNC pin provide a pulse on frame boundaries (RCR2.3=0). If the user
wishes to obtain pulses at the frame boundary, then RCR2.4 must be set to zero and if the
user wishes to have pulses occur at the multiframe boundary, then RCR2.4 must be set to
one. The framer will always indicate frame boundaries via the RFSYNC output whether the
elastic store is enabled or not. If the elastic store is enabled, then multiframe boundaries will
be indicated via the RMSYNC output. If the user selects to apply a 2.048 MHz clock to the
RSYSCLK pin, then the data output at RSER will be forced to all ones every fourth
channel. Hence channels 1 (except for the MSB), 5, 9, 13, 17, 21, 25, and 29 (timeslots 0,
4, 8, 12, 16, 20, 24, and 28) will be forced to a one. The F–bit will be passed in the MSB
of channel 1. Also, in 2.048 MHz applications, the RCHBLK output will be forced high
during the same channels as the RSER pin. See Section 23 for more details. This is useful
in T1 to CEPT (E1) conversion applications. If the 386–bit elastic buffer either fills or
empties, a controlled slip will occur. If the buffer empties, then a full frame of data (193 bits)
will be repeated at RSER and the SR1.4 and RIR1.3 bits will be set to a one. If the buffer
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