參數(shù)資料
型號: DS21FT42
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 74/145頁
文件大?。?/td> 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1234
18. HDLC CONTROLLER
The DS21Q42 has an enhanced HDLC controller configurable for use with the Facilities
Data Link or DS0s. There are 64 byte buffers in both the transmit and receive paths. The
user can select any DS0 or multiple DS0s as well as any specific bits within the DS0(s) to
pass through the HDLC controller. See Figure 24-15 for details on formatting the transmit
side. Note that TBOC.6 = 1 and TDC1.7 = 1 cannot exist without corrupting the data in
the FDL. For use with the FDL, see section 19.1. See Table 18-1 for configuring the
transmit HDLC controller.
Four new registers were added for the enhanced functionality of the HDLC controller; RDC1,
RDC2, TDC1, and TDC2. Note that the BOC controller is functional when the HDLC
controller is used for DS0s. Section 19 contains all of the HDLC and BOC registers and
information on FDL/Fs Extraction and Insertion with and without the HDLC controller.
Transmit HDLC Configuration
Table 18-1
Function
TBOC.6
0
1
0
TDC1.7
1
0
0
TCR1.2
1 or 0
1
1 or 0
DS0(s)
FDL
Disable
18.1
HDLC for DS0s
When using the HDLC controllers for DS0s, the same registers shown in section 19 will be
used except for the TBOC and RBOC registers and bits HCR.7, HSR.7, and HIMR.7. As a
basic guideline for interpreting and sending HDLC messages and BOC messages, the
following sequences can be applied.
Receive a HDLC Message
1. Enable RPS interrupts
2. Wait for interrupt to occur
3. Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt
4. Read RHIR to obtain REMPTY status
a. If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the
FIFO
a1. If CBYTE=0 then skip to step 5
a2. If CBYTE=1 then skip to step 7
b. If REMPTY=1, then skip to step 6
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