參數(shù)資料
型號： DS21FT42
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 103/145頁
文件大?。?/td> 466K
代理商： DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/103
Instruction Codes For The DS21352/552 IEEE 1149.1 Architecture
Table 23-1
Instruction
Selected Register
Boundary Scan
Bypass
Boundary Scan
Boundary Scan
Boundary Scan
Device Identification
Instruction Codes
010
111
000
011
100
001
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two
functions. The digital I/Os of the DS21Q42 can be sampled at the boundary scan register
without interfering with the normal operation of the device by using the Capture-DR state.
SAMPLE/PRELOAD also allows the DS21Q42 to shift data into the boundary scan register
via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS21Q42. When the EXTEST
instruction is latched in the instruction register, the following actions occur. Once enabled
via the Update-IR state, the parallel outputs of all digital output pins will be driven. The
boundary scan register will be connected between JTDI and JTDO. The Capture-DR will
sample all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI
connects to JTDO through the one-bit bypass test register. This allows data to pass from
JTDI to JTDO not affecting the device’s normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the
Identification Test register is selected. The device identification code will be loaded into the
Identification register on the rising edge of JTCLK following entry into the Capture-DR
state. Shift-DR can be used to shift the identification code out serially via JTDO. During
Test-Logic-Reset, the identification code is forced into the instruction register’s parallel
output. The ID code will always have a ‘1’ in the LSB position. The next 11 bits identify
the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for
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參數(shù)描述
DS21FT42N 功能描述:網(wǎng)絡控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44+ 功能描述:網(wǎng)絡控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N 功能描述:網(wǎng)絡控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N+ 功能描述:網(wǎng)絡控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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