136
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Y specifies which halfword of the source register
Rm
is used as the second multiply operand.
If
Y
is B, then the bottom halfword (bits [15:0]) of
Rm
is used.
If
Y
is T, then the top halfword (bits [31:16]) of
Rm
is used.
cond
is an optional condition code, see
“Conditional Execution”
.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SMULBB, SMULTB, SMULBT and SMULTT instructions interprets the values from
Rn
and
Rm
as four signed 16-bit
integers. These instructions:
Multiplies the specified signed halfword, Top or Bottom, values from
Rn
and
Rm
.
Writes the 32-bit result of the multiplication in
Rd.
The SMULWT and SMULWB instructions interprets the values from
Rn
as a 32-bit signed integer and
Rm
as two
halfword 16-bit signed integers. These instructions:
Multiplies the first operand and the top, T suffix, or the bottom, B suffix, halfword of the second operand.
Writes the signed most significant 32 bits of the 48-bit result in the destination register.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi
and
RdLo
must be different registers.
Examples
SMULBT R0, R4, R5 ; Multiplies the bottom halfword of R4 with the
; top halfword of R5, multiplies results and
; writes to R0
SMULBB R0, R4, R5 ; Multiplies the bottom halfword of R4 with the
; bottom halfword of R5, multiplies results and
; writes to R0
SMULTT R0, R4, R5 ; Multiplies the top halfword of R4 with the top
; halfword of R5, multiplies results and writes
; to R0
SMULTB R0, R4, R5 ; Multiplies the top halfword of R4 with the
; bottom halfword of R5, multiplies results and
; and writes to R0
SMULWT R4, R5, R3 ; Multiplies R5 with the top halfword of R3,
; extracts top 32 bits and writes to R4
SMULWB R4, R5, R3 ; Multiplies R5 with the bottom halfword of R3,
; extracts top 32 bits and writes to R4.
12.6.6.11 UMULL, UMLAL, SMULL, and SMLAL
Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result.
Syntax
op
{
cond
}
RdLo
,
RdHi
,
Rn
,
Rm
where:
op
is one of:
UMULL Unsigned Long Multiply.
UMLAL Unsigned Long Multiply, with Accumulate.
SMULL Signed Long Multiply.
SMLAL Signed Long Multiply, with Accumulate.