43
SAM4CP [DATASHEET]
43051E–ATPL–08/14
11.2
Peripheral DMA Controller
Two Peripheral DMA Controllers (PDC) are available:
PDC0: dedicated to peripherals on APB0
PDC1: dedicated to peripherals on APB1
Features of the PDC include:
Data transfer handling between peripherals and memories
Low bus arbitration overhead
One Master Clock cycle needed for a transfer from memory to peripheral
Two Master Clock cycles needed for a transfer from peripheral to memory
Next Pointer management for reducing interrupt latency requirement
Note that Peripheral DMA 0 on Matrix 0 cannot access SRAM1 or SRAM2. Peripheral DMA 1 on Matrix 1 cannot access
SRAM0.
26
TC3
X
X
Timer/Counter 3 (Sub-system 0 Clock)
27
TC4
X
X
Timer/Counter 4 (Sub-system 0 Clock)
28
TC5
X
X
Timer/Counter 5 (Sub-system 0 Clock)
29
ADC
X
X
Analog To Digital Converter (Sub-system 0 Clock)
30
ARM
X
-
FPU signals (only on CM4P1 core): FPIXC, FPOFC,
FPUFC, FPIOC, FPDZC, FPIDC, FPIXC
31
IPC0
X
X
Interprocessor communication 0 (Sub-system 0
Clock)
32
SLCDC
X
X
Segment LCD Controller (Sub-system 0 Clock)
33
TRNG
X
X
True Random Generator (Sub-system 0 Clock)
34
ICM
X
X
Integrity Check Module (Sub-system 0 Clock)
35
CPKCC
X
X
Classical Public Key Cryptography Controller (Sub-
system 0 Clock)
36
AES
X
X
Advanced Enhanced Standard (Sub-system 0 Clock)
37
PIOC
X
X
Parallel I/O Controller C (Sub-system 1 Clock)
38
UART1
X
X
UART 1 (Sub-system 1 Clock)
39
IPC1
X
X
Interprocessor communication 1 (Sub-system 1
Clock)
40
SPI1
X
X
Serial Peripheral Interface 1 (Sub-system 1 Clock)
41
PWM
X
X
Pulse Width Modulation (Sub-system 1 Clock)
42
SRAM
-
X
SRAM1 (I/D Code bus of CM4P1), SRAM2 (System
bus of CM4P1) (Sub-system 1 Clock)
43
-
-
-
Reserved
Table 11-1.
Peripheral Identifiers (Continued)
Instance ID
Instance Name
NVIC Interrupt
PMC
Clock Control
Instance Description