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型號(hào)：	E5550F-S8
廠商：	TEMIC SEMICONDUCTORS
元件分類：	通信及網(wǎng)絡(luò)
英文描述：	SPECIALTY TELECOM CIRCUIT, PDSO8
文件頁數(shù)：	722/1069頁
文件大?。?/td>	14303K
代理商：	E5550F-S8

SAM4CP [DATASHEET]

43051E–ATPL–08/14

Figure 35-7.

Parity Error

35.5.2.6 Receiver Framing Error

When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is

also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same time the

RXRDY bit is set. The FRAME bit remains high until the control register (UART_CR) is written with the bit RSTSTA at 1.

Figure 35-8.

Receiver Framing Error

35.5.2.7 Receiver Digital Filter

The UART embeds a digital filter on the receive line. It is disabled by default and can be enabled by writing a logical 1 in

the FILTER bit of UART_MR. When enabled, the receive line is sampled using the 16x bit clock and a three-sample filter

(majority 2 over 3) determines the value of the line.

35.5.3 Transmitter

35.5.3.1 Transmitter Reset, Enable and Disable

After device reset, the UART transmitter is disabled and must be enabled before being used. The transmitter is enabled

by writing UART_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the

Transmit Holding Register (UART_THR) before actually starting the transmission.

The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1. If the transmitter is not

operating, it is immediately stopped. However, if a character is being processed into the internal shift register and/or a

character has been written in the UART_THR, the characters are completed before the transmitter is actually stopped.

The programmer can also put the transmitter in its reset state by writing the UART_CR with the bit RSTTX at 1. This

immediately stops the transmitter, whether or not it is processing characters.

35.5.3.2 Transmit Format

The UART transmitter drives the pin UTXD at the baud rate clock speed. The line is driven depending on the format

defined in UART_MR and the data stored in the internal shift register. One start bit at level 0, then the 8 data bits, from

the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown in the

following figure. The field PARE in UART_MR defines whether or not a parity bit is shifted out. When a parity bit is

enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit.

Wrong Parity Bit

Detected at 0

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
E5551A-DIT	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DOW	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-FP008	制造商:未知廠家制造商全稱:未知廠家功能描述:TRANSPONDER\|CMOS\|SOP\|8PIN\|PLASTIC
E5552	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E555423	制造商:Elo Touch Solutions Inc 功能描述:1729L, 17-INCH LCD, CARROLLTOUCH, USB CONTROLLER, GRAY - Bulk

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