480
SAM4CP [DATASHEET]
43051E–ATPL–08/14
27.8.3.3.7 Header EVM Registers
Name:
TXRXBUF_EVM_HD_RX0
Address:
0xFDA3 - 0xFDA4
Access:
Read-only
Reset:
0x0000
This register stores the maximum EVM (Error Vector Magnitude) measured in the reception of the last message
header in BUF_RX0. The 7 msb, TXRXBUF_EVM_HD_RX0 (15:9), represent the integer part in %, being the
TXRXBUF_EVM_HD_RX0 (8:0) bits the fractional part if more precision were required.
This register is used by the physical layer for being in accordance with PRIME specification.
Name:
TXRXBUF_EVM_HD_RX1
Address:
0xFDA5 - 0xFDA6
Access:
Read-only
Reset:
0x0000
This register stores the maximum EVM (Error Vector Magnitude) measured in the reception of the last message
header in BUF_RX1. The 7 msb, TXRXBUF_EVM_HD_RX1 (15:9), represent the integer part in %, being the
TXRXBUF_EVM_HD_RX1 (8:0) bits the fractional part if more precision were required.
This register is used by the physical layer for being in accordance with PRIME specification.
Name:
TXRXBUF_EVM_HD_RX2
Address:
0xFDA7 - 0xFDA8
Access:
Read-only
Reset:
0x0000
This register stores the maximum EVM (Error Vector Magnitude) measured in the reception of the last message
header in BUF_RX2. The 7 msb, TXRXBUF_EVM_HD_RX2 (15:9), represent the integer part in %, being the
TXRXBUF_EVM_HD_RX2 (8:0) bits the fractional part if more precision were required.
This register is used by the physical layer for being in accordance with PRIME specification.
15
14
13
12
11
10
9
8
TXRXBUF_EVM_HD_RX0 (15:8)
7
6
5
4
3
2
1
0
TXRXBUF_EVM_HD_RX0 (7:0)
15
14
13
12
11
10
9
8
TXRXBUF_EVM_HD_RX1 (15:8)
7
6
5
4
3
2
1
0
TXRXBUF_EVM_HD_RX1 (7:0)
15
14
13
12
11
10
9
8
TXRXBUF_EVM_HD_RX2 (15:8)
7
6
5
4
3
2
1
0
TXRXBUF_EVM_HD_RX2 (7:0)